Skip to main content

Module wire

Module wire 

Source
Expand description

FIDL wire type definitions and implementations.

Modules§

fuchsia
Fuchsia-specific FIDL wire type definitions and implementations.

Structs§

Box
A boxed (optional) FIDL value.
Float32
A wire-encoded f32
Float64
A wire-encoded f64
Int16
A wire-encoded i16
Int32
A wire-encoded i32
Int64
A wire-encoded i64
IntoIter
An iterator over the items of a WireVector.
OptionalString
An optional FIDL string
OptionalVector
An optional FIDL vector
Result
A FIDL result union.
String
A FIDL string
Table
A FIDL table
Uint16
A wire-encoded u16
Uint32
A wire-encoded u32
Uint64
A wire-encoded u64
Union
A raw FIDL union
Vector
A FIDL vector

Enums§

EmptyStruct
An empty struct’s wire representation. C/C++ memory layout rules (and hence FIDL wire rules) require every object to have a unique address so we have to make a single, tiny type for empty structs.

Unions§

Envelope
A FIDL envelope
Pointer
A raw FIDL pointer