Struct BufferMemoryConstraints

pub struct BufferMemoryConstraints {
    pub min_size_bytes: Option<u64>,
    pub max_size_bytes: Option<u64>,
    pub physically_contiguous_required: Option<bool>,
    pub secure_required: Option<bool>,
    pub cpu_domain_supported: Option<bool>,
    pub ram_domain_supported: Option<bool>,
    pub inaccessible_domain_supported: Option<bool>,
    pub permitted_heaps: Option<Vec<Heap>>,
    /* private fields */
}

Fields

min_size_bytes: Option<u64>

un-set is treated as 1

max_size_bytes: Option<u64>

un-set is treated as 0xFFFFFFFFFFFFFFFF.

physically_contiguous_required: Option<bool>

When false, physical pages of a buffer VMO can be non-contiguous. When true, physical pages of a buffer VMO must be sequentially contiguous. A client that doesn’t require physically contiguous VMOs must still accept physically contiguous VMOs or “physical” VMOs.

secure_required: Option<bool>

If true, the participant requires secure memory.

When aggregating BufferCollectionConstraints, these values boolean-OR.

cpu_domain_supported: Option<bool>

When true (or when BufferMemoryConstraints is not present), the participant is ok with sysmem selecting the CPU domain.

If the CPU domain is selected, participants must ensure the CPU can read or write data to the buffer without cache operations outside of the participant.

In other words, if a producer participant DMAs data directly to RAM on a non-cache-coherent architecture such as arm, the producer must ensure the CPU cache is clean wrt. the buffer before the DMA write, and invalidate the CPU cache after the DMA write and before indicating that the buffer is ready to any other participant. If a consumer participant DMAs data directly from RAM on a non-cache-coherent architecture such as arm, the consumer must flush the CPU cache wrt the buffer before the DMA read.

CPU-only participants that don’t do any DMA can just write and read the buffers (when they should) without needing to do any CPU cache ops.

ram_domain_supported: Option<bool>

When true, the participant is ok with sysmem selecting the RAM domain.

If the RAM domain is selected, producer data must be available in RAM (with CPU cache state such that the RAM data won’t get corrupted by a dirty CPU cache line writing incorrect data to RAM), and a consumer reading using the CPU must invalidate CPU cache before reading (the producer doesn’t guarantee zero stale “clean” cache lines).

In other words, if a producer participant uses the CPU to write data on a non-cache-coherent architecture such as arm, the producer must flush the data to RAM before indicating to another participant that the buffer is ready. If a consumer participant uses the CPU to read data on a non-cache-coherent architecture such as arm, the participant must invalidate (typically flush+invalidate with knowledge that no cache lines are dirty) the CPU cache before reading the buffer.

RAM-only participants that don’t do any CPU accesses to a buffer can just do DMA to/from the buffers (when they should) without needing to do any CPU cache ops.

inaccessible_domain_supported: Option<bool>

When true, the participant is ok with sysmem selecting the INACCESSIBLE domain.

If the INACCESSIBLE domain is selected, CPU reads and writes of the data are prevented. Attempts to read/write the data with the CPU may result in UB and/or process termination.

If the INACCESSIBLE domain is selected, participants must only operate on the data using DMAs performed by HW, or platform-specific DMA-like requests to a secure environment (which will do the needed CPU cache ops similar to how a RAM domain participant would operate).

Secure heaps only support INACCESSIBLE domain, and will fail allocation if any participant with BufferUsage other than NONE_USAGE does not set inaccessible_domain_supported to true.

When the INACCESSIBLE domain is selected, participants (outside of secure/DRM environments) should not attempt to map buffers, and should not attempt to perform any CPU cache ops. In this respect, this domain is similar to RAM domain with all participants only doing DMA and no participant(s) doing CPU accesses.

permitted_heaps: Option<Vec<Heap>>

Which heaps are acceptable to the participant. Participants that don’t care which heap memory is allocated on should leave this field un-set. A secure heap is only selected if all participants explicitly indicate that the secure heap is acceptable via heap_permitted, or specify NONE_USAGE.

Trait Implementations

impl Clone for BufferMemoryConstraints

fn clone(&self) -> BufferMemoryConstraints

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for BufferMemoryConstraints

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl<D> Decode<BufferMemoryConstraints, D> for BufferMemoryConstraints

where D: ResourceDialect,

fn new_empty() -> BufferMemoryConstraints

Creates a valid instance of Self. The specific value does not matter, since it will be overwritten by decode.

unsafe fn decode( &mut self, decoder: &mut Decoder<'_, D>, offset: usize, depth: Depth, ) -> Result<(), Error>

Decodes an object of type T from the decoder’s buffers into self.

impl Default for BufferMemoryConstraints

fn default() -> BufferMemoryConstraints

Returns the “default value” for a type.

impl<D> Encode<BufferMemoryConstraints, D> for &BufferMemoryConstraints

where D: ResourceDialect,

unsafe fn encode( self, encoder: &mut Encoder<'_, D>, offset: usize, depth: Depth, ) -> Result<(), Error>

Encodes the object into the encoder’s buffers. Any handles stored in the object are swapped for Handle::INVALID.

impl PartialEq for BufferMemoryConstraints

fn eq(&self, other: &BufferMemoryConstraints) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl TypeMarker for BufferMemoryConstraints

type Owned = BufferMemoryConstraints

The owned Rust type which this FIDL type decodes into.

fn inline_align(_context: Context) -> usize

Returns the minimum required alignment of the inline portion of the encoded object. It must be a (nonzero) power of two.

fn inline_size(_context: Context) -> usize

Returns the size of the inline portion of the encoded object, including padding for alignment. Must be a multiple of inline_align.

fn encode_is_copy() -> bool

Returns true if the memory layout of Self::Owned matches the FIDL wire format and encoding requires no validation. When true, we can optimize encoding arrays and vectors of Self::Owned to a single memcpy.

fn decode_is_copy() -> bool

Returns true if the memory layout of Self::Owned matches the FIDL wire format and decoding requires no validation. When true, we can optimize decoding arrays and vectors of Self::Owned to a single memcpy.

impl ValueTypeMarker for BufferMemoryConstraints

type Borrowed<'a> = &'a BufferMemoryConstraints

The Rust type to use for encoding. This is a particular Encode<Self> type cheaply obtainable from &Self::Owned. There are three cases:

fn borrow( value: &<BufferMemoryConstraints as TypeMarker>::Owned, ) -> <BufferMemoryConstraints as ValueTypeMarker>::Borrowed<'_>

Cheaply converts from &Self::Owned to Self::Borrowed.

impl Persistable for BufferMemoryConstraints

impl StructuralPartialEq for BufferMemoryConstraints