pub struct Topology {
pub id: Option<u64>,
pub processing_elements_edge_pairs: Option<Vec<EdgePair>>,
/* private fields */
}
Expand description
A Topology
specifies how processing elements are arranged within the hardware.
Fields§
§id: Option<u64>
Unique ID for this topology. The scope of this id is only within the SignalProcessing
protocol lifespan, i.e. until the channel associated with the protocol is closed.
Required.
processing_elements_edge_pairs: Option<Vec<EdgePair>>
Vector of processing elements edge pairs that specify connections between elements. Processing elements are connected by edge pairs, to form multi-element pipelines. A Topology can contain more than one distinct pipeline: the Topology need not be a single interconnected sequence (e.g. Topology A->B->C D->E->F is valid).
To define multiple possible configurations where one possibility can be selected by the
client, return multiple Topology
entries in GetTopologies
.
If a device does support multiple Topology entries, then each specific Topology is not required to include every Element. However, every element must be included in at least one Topology.
Within each Topology, every sequence of connected elements must begin with an element of type DAI_INTERCONNECT or RING_BUFFER, and must end with an element of type DAI_INTERCONNECT or RING_BUFFER.
An DAI_INTERCONNECT element is permitted to be the endpoint for an element sequence, but a
RING_BUFFER is required to be one. If a certain RING_BUFFER element is listed in an EdgeList
entry as a processing_element_id_from
, then within that Topology it must not be listed in
any EdgeList entry as a processing_element_id_to
(and vice versa).
Required. Must contain at least one entry.
Trait Implementations§
Source§impl<D: ResourceDialect> Decode<Topology, D> for Topology
impl<D: ResourceDialect> Decode<Topology, D> for Topology
Source§impl TypeMarker for Topology
impl TypeMarker for Topology
Source§fn inline_align(_context: Context) -> usize
fn inline_align(_context: Context) -> usize
Source§fn inline_size(_context: Context) -> usize
fn inline_size(_context: Context) -> usize
inline_align
.§fn encode_is_copy() -> bool
fn encode_is_copy() -> bool
Self::Owned
matches the FIDL wire
format and encoding requires no validation. When true, we can optimize
encoding arrays and vectors of Self::Owned
to a single memcpy. Read more§fn decode_is_copy() -> bool
fn decode_is_copy() -> bool
Self::Owned
matches the FIDL wire
format and decoding requires no validation. When true, we can optimize
decoding arrays and vectors of Self::Owned
to a single memcpy.