1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
// Copyright 2017 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

//! Type-safe bindings for Zircon port objects.

use crate::{
    guest, ok, sys, AsHandleRef, GPAddr, Handle, HandleBased, HandleRef, MonotonicInstant, Signals,
    Status, VcpuContents,
};
use bitflags::bitflags;
use std::mem;

/// An object representing a Zircon
/// [port](https://fuchsia.dev/fuchsia-src/concepts/objects/port.md).
///
/// As essentially a subtype of `Handle`, it can be freely interconverted.
#[derive(Debug, Eq, PartialEq, Ord, PartialOrd, Hash)]
#[repr(transparent)]
pub struct Port(Handle);
impl_handle_based!(Port);

bitflags! {
    /// Options that may be used when creating a `Port`.
    pub struct PortOptions: u32 {
        const BIND_TO_INTERRUPT = sys::ZX_PORT_BIND_TO_INTERRUPT;
    }
}

/// The contents of a `Packet`.
#[derive(Debug, Copy, Clone)]
pub enum PacketContents {
    /// A user-generated packet.
    User(UserPacket),
    /// A one-shot signal packet generated via `object_wait_async`.
    SignalOne(SignalPacket),
    /// A guest bell packet
    GuestBell(GuestBellPacket),
    /// A guest mem packet
    GuestMem(GuestMemPacket),
    /// A guest I/O packet
    GuestIo(GuestIoPacket),
    /// A guest VCPU packet
    GuestVcpu(GuestVcpuPacket),
    /// Pager packets
    Pager(PagerPacket),
    /// Interrupt packets
    Interrupt(InterruptPacket),
    /// power transition request packets.
    /// This is gated under syscalls-next.h
    PowerTransition(PowerTransitionPacket),

    #[doc(hidden)]
    __Nonexhaustive,
}

/// Contents of a user packet (one sent by `port_queue`). This is a type-safe wrapper for
/// [zx_packet_user_t](https://fuchsia.dev/fuchsia-src/reference/syscalls/port_wait.md).
#[derive(Debug, Default, Copy, Clone)]
pub struct UserPacket(sys::zx_packet_user_t);

/// Contents of a signal packet (one generated by the kernel). This is a type-safe wrapper for
/// [zx_packet_signal_t](https://fuchsia.dev/fuchsia-src/reference/syscalls/port_wait.md).
#[derive(Debug, Copy, Clone)]
pub struct SignalPacket(sys::zx_packet_signal_t);

/// Contents of a guest bell packet generated by the kernel. This is a type-safe wrapper for
/// zx_packet_guest_bell_t
#[derive(Debug, Copy, Clone)]
pub struct GuestBellPacket(sys::zx_packet_guest_bell_t);

/// Contents of a guest memory packet generated by the kernel. This is a type-safe wrapper for
/// zx_packet_guest_memory_t
#[derive(Debug, Copy, Clone)]
pub struct GuestMemPacket(sys::zx_packet_guest_mem_t);

/// Contents of a guest I/O packet generated by the kernel. This is a type-safe wrapper for
/// zx_packet_guest_io_t
#[derive(Debug, Copy, Clone)]
pub struct GuestIoPacket(sys::zx_packet_guest_io_t);

/// Contents of a guest VCPU packet generated by the kernel. This is a type-safe wrapper for
/// zx_packet_guest_vcpu_t
#[derive(Debug, Copy, Clone)]
pub struct GuestVcpuPacket(sys::zx_packet_guest_vcpu_t);

/// Contents of a pager packet generated by the kernel. This is a type-safe wrapper for
/// zx_packet_page_request_t
#[derive(Debug, Copy, Clone)]
pub struct PagerPacket(sys::zx_packet_page_request_t);

/// Contents of an interrupt packet (one received because of an interrupt bound to this port).
/// This is a type-safe wrapper for zx_packet_interrupt_t.
#[derive(Debug, Copy, Clone)]
pub struct InterruptPacket(sys::zx_packet_interrupt_t);

/// Contents of a power transition packet generated by the kernel. This is a type-safe wrapper for
/// zx_packet_processor_power_level_transition_request_t
#[derive(Debug, Copy, Clone)]
pub struct PowerTransitionPacket(sys::zx_packet_processor_power_level_transition_request_t);

/// A packet sent through a port. This is a type-safe wrapper for
/// [zx_port_packet_t](https://fuchsia.dev/fuchsia-src/reference/syscalls/port_wait.md).
#[derive(PartialEq, Eq, Debug)]
pub struct Packet(pub(crate) sys::zx_port_packet_t);

impl Packet {
    /// Creates a new packet with `UserPacket` data.
    pub fn from_user_packet(key: u64, status: i32, user: UserPacket) -> Packet {
        Packet(sys::zx_port_packet_t {
            key: key,
            packet_type: sys::zx_packet_type_t::ZX_PKT_TYPE_USER,
            status: status,
            union: user.0,
        })
    }

    /// Creates a new packet with `GuestMemPacket` data.
    pub fn from_guest_mem_packet(key: u64, status: i32, mem: GuestMemPacket) -> Packet {
        let mut raw = sys::zx_port_packet_t {
            key,
            packet_type: sys::zx_packet_type_t::ZX_PKT_TYPE_GUEST_MEM,
            status,
            union: Default::default(),
        };
        // transmute_copy doesn't work because the mem packet is too small and
        // transmute_copy requires that Dst is not larger than Src.
        //
        // Note that at the time of writing this only applied to arm64 builds;
        // x64 builds work fine with transmute_copy. This is because the
        // underlying `zx_packet_guest_mem_t` struct has a different size on x64
        // vs arm64.
        let bytes: &[u8; std::mem::size_of::<sys::zx_packet_guest_mem_t>()] =
            unsafe { mem::transmute(&mem.0) };
        raw.union[0..std::mem::size_of::<sys::zx_packet_guest_mem_t>()].copy_from_slice(bytes);
        Packet(raw)
    }

    /// Creates a new packet with `GuestIoPacket` data.
    pub fn from_guest_io_packet(key: u64, status: i32, io: GuestIoPacket) -> Packet {
        let mut raw = sys::zx_port_packet_t {
            key,
            packet_type: sys::zx_packet_type_t::ZX_PKT_TYPE_GUEST_IO,
            status,
            union: Default::default(),
        };
        // transmute_copy doesn't work because the io packet is too small and
        // transmute_copy requires that Dst is not larger than Src.
        let bytes: &[u8; std::mem::size_of::<sys::zx_packet_guest_io_t>()] =
            unsafe { mem::transmute(&io.0) };
        raw.union[0..std::mem::size_of::<sys::zx_packet_guest_io_t>()].copy_from_slice(bytes);
        Packet(raw)
    }

    /// Creates a new packet with `GuestVcpuPacket` data.
    pub fn from_guest_vcpu_packet(key: u64, status: i32, vcpu: GuestVcpuPacket) -> Packet {
        Packet(sys::zx_port_packet_t {
            key,
            packet_type: sys::zx_packet_type_t::ZX_PKT_TYPE_GUEST_VCPU,
            status,
            union: unsafe { mem::transmute_copy(&vcpu.0) },
        })
    }

    /// Creates a new packet with `PowerTransitionPacket` data.
    pub fn from_power_transition_packet(
        key: u64,
        status: i32,
        power_transition_packet: PowerTransitionPacket,
    ) -> Packet {
        Packet(sys::zx_port_packet_t {
            key: key,
            packet_type:
                sys::zx_packet_type_t::ZX_PKT_TYPE_PROCESSOR_POWER_LEVEL_TRANSITION_REQUEST,
            status: status,
            union: unsafe { mem::transmute_copy(&power_transition_packet.0) },
        })
    }

    /// The packet's key.
    pub fn key(&self) -> u64 {
        self.0.key
    }

    /// The packet's status.
    // TODO: should this type be wrapped?
    pub fn status(&self) -> i32 {
        self.0.status
    }

    /// The contents of the packet.
    pub fn contents(&self) -> PacketContents {
        match self.0.packet_type {
            sys::zx_packet_type_t::ZX_PKT_TYPE_USER => {
                PacketContents::User(UserPacket(self.0.union))
            }

            sys::zx_packet_type_t::ZX_PKT_TYPE_SIGNAL_ONE => {
                PacketContents::SignalOne(SignalPacket(unsafe {
                    mem::transmute_copy(&self.0.union)
                }))
            }

            sys::zx_packet_type_t::ZX_PKT_TYPE_GUEST_BELL => {
                PacketContents::GuestBell(GuestBellPacket(unsafe {
                    mem::transmute_copy(&self.0.union)
                }))
            }

            sys::zx_packet_type_t::ZX_PKT_TYPE_GUEST_MEM => {
                PacketContents::GuestMem(GuestMemPacket(unsafe {
                    mem::transmute_copy(&self.0.union)
                }))
            }

            sys::zx_packet_type_t::ZX_PKT_TYPE_GUEST_IO => {
                PacketContents::GuestIo(GuestIoPacket(unsafe {
                    mem::transmute_copy(&self.0.union)
                }))
            }

            sys::zx_packet_type_t::ZX_PKT_TYPE_GUEST_VCPU => {
                PacketContents::GuestVcpu(GuestVcpuPacket(unsafe {
                    mem::transmute_copy(&self.0.union)
                }))
            }

            sys::zx_packet_type_t::ZX_PKT_TYPE_PAGE_REQUEST => {
                PacketContents::Pager(PagerPacket(unsafe { mem::transmute_copy(&self.0.union) }))
            }

            sys::zx_packet_type_t::ZX_PKT_TYPE_INTERRUPT => {
                PacketContents::Interrupt(InterruptPacket(unsafe {
                    mem::transmute_copy(&self.0.union)
                }))
            }

            sys::zx_packet_type_t::ZX_PKT_TYPE_PROCESSOR_POWER_LEVEL_TRANSITION_REQUEST => {
                PacketContents::PowerTransition(PowerTransitionPacket(unsafe {
                    mem::transmute_copy(&self.0.union)
                }))
            }

            _ => panic!("unexpected packet type"),
        }
    }
}

impl UserPacket {
    pub fn from_u8_array(val: [u8; 32]) -> UserPacket {
        UserPacket(val)
    }

    pub fn as_u8_array(&self) -> &[u8; 32] {
        &self.0
    }

    pub fn as_mut_u8_array(&mut self) -> &mut [u8; 32] {
        &mut self.0
    }
}

impl SignalPacket {
    /// The signals used in the call to `object_wait_async`.
    pub fn trigger(&self) -> Signals {
        Signals::from_bits_truncate(self.0.trigger)
    }

    /// The observed signals.
    pub fn observed(&self) -> Signals {
        Signals::from_bits_truncate(self.0.observed)
    }

    /// A per object count of pending operations.
    pub fn count(&self) -> u64 {
        self.0.count
    }

    /// Get a reference to the raw underlying packet.
    pub fn raw_packet(&self) -> &sys::zx_packet_signal_t {
        &self.0
    }
}

impl GuestBellPacket {
    /// The guest physical address that was accessed that triggered the bell.
    pub fn addr(&self) -> GPAddr {
        GPAddr(self.0.addr)
    }
}

impl GuestMemPacket {
    pub fn from_raw(mem: sys::zx_packet_guest_mem_t) -> GuestMemPacket {
        GuestMemPacket(mem)
    }

    /// The guest physical address that was accessed that triggered this signal.
    pub fn addr(&self) -> GPAddr {
        GPAddr(self.0.addr)
    }
}

#[cfg(target_arch = "aarch64")]
impl GuestMemPacket {
    /// Size of the access.
    ///
    /// Returns `None` should it find and invalid size in the packet.
    pub fn access_size(&self) -> Option<guest::MemAccessSize> {
        match self.0.access_size {
            1 => Some(guest::MemAccessSize::Bits8),
            2 => Some(guest::MemAccessSize::Bits16),
            4 => Some(guest::MemAccessSize::Bits32),
            8 => Some(guest::MemAccessSize::Bits64),
            _ => None,
        }
    }

    /// Whether or not data should be sign extended.
    pub fn sign_extend(&self) -> bool {
        self.0.sign_extend
    }

    /// Register number of the Rt operand of the faulting instruction.
    pub fn reg(&self) -> u8 {
        self.0.xt
    }

    /// For `AccessType::Write` this is the data that was being written.
    pub fn data(&self) -> Option<guest::MemData> {
        if let guest::AccessType::Write = self.access_type() {
            self.access_size().map(|size| match size {
                guest::MemAccessSize::Bits8 => guest::MemData::Data8(self.0.data as u8),
                guest::MemAccessSize::Bits16 => guest::MemData::Data16(self.0.data as u16),
                guest::MemAccessSize::Bits32 => guest::MemData::Data32(self.0.data as u32),
                guest::MemAccessSize::Bits64 => guest::MemData::Data64(self.0.data),
            })
        } else {
            None
        }
    }

    /// Type of access (read or write).
    pub fn access_type(&self) -> guest::AccessType {
        match self.0.read {
            true => guest::AccessType::Read,
            false => guest::AccessType::Write,
        }
    }
}

#[cfg(target_arch = "x86_64")]
impl GuestMemPacket {
    /// Specifies the default operand size encoded by the CS descriptor.
    ///
    /// Returns a `None` should it find an invalid size in the packet.
    pub fn default_operand_size(&self) -> Option<guest::CSDefaultOperandSize> {
        // TODO: use try_from when it is stable.
        match self.0.default_operand_size {
            2 => Some(guest::CSDefaultOperandSize::Bits16),
            4 => Some(guest::CSDefaultOperandSize::Bits32),
            _ => None,
        }
    }
}

impl GuestIoPacket {
    pub fn from_raw(io: sys::zx_packet_guest_io_t) -> GuestIoPacket {
        GuestIoPacket(io)
    }

    /// First port number of the attempted access
    pub fn port(&self) -> u16 {
        self.0.port
    }

    /// Size of the access.
    ///
    /// Returns `None` should it find an invalid size in the packet.
    pub fn access_size(&self) -> Option<guest::PortAccessSize> {
        match self.0.access_size {
            1 => Some(guest::PortAccessSize::Bits8),
            2 => Some(guest::PortAccessSize::Bits16),
            4 => Some(guest::PortAccessSize::Bits32),
            _ => None,
        }
    }

    /// Type of access (read or write).
    pub fn access_type(&self) -> guest::AccessType {
        match self.0.input {
            true => guest::AccessType::Read,
            false => guest::AccessType::Write,
        }
    }

    /// For `PortAccessType::Write` this is the data that was being written.
    pub fn data(&self) -> Option<guest::PortData> {
        #[repr(C)]
        union DataUnion {
            bit8: [u8; 4],
            bit16: [u16; 2],
            bit32: [u32; 1],
        }
        if let guest::AccessType::Write = self.access_type() {
            unsafe {
                let data = &DataUnion { bit8: self.0.data };
                self.access_size().map(|size| match size {
                    guest::PortAccessSize::Bits8 => guest::PortData::Data8(data.bit8[0]),
                    guest::PortAccessSize::Bits16 => guest::PortData::Data16(data.bit16[0]),
                    guest::PortAccessSize::Bits32 => guest::PortData::Data32(data.bit32[0]),
                })
            }
        } else {
            None
        }
    }
}

impl GuestVcpuPacket {
    pub fn from_raw(vcpu: sys::zx_packet_guest_vcpu_t) -> GuestVcpuPacket {
        GuestVcpuPacket(vcpu)
    }

    pub fn contents(&self) -> VcpuContents {
        match self.0.r#type {
            sys::zx_packet_guest_vcpu_type_t::ZX_PKT_GUEST_VCPU_INTERRUPT => unsafe {
                VcpuContents::Interrupt {
                    mask: self.0.union.interrupt.mask,
                    vector: self.0.union.interrupt.vector,
                }
            },
            sys::zx_packet_guest_vcpu_type_t::ZX_PKT_GUEST_VCPU_STARTUP => unsafe {
                VcpuContents::Startup {
                    id: self.0.union.startup.id,
                    entry: self.0.union.startup.entry,
                }
            },
            sys::zx_packet_guest_vcpu_type_t::ZX_PKT_GUEST_VCPU_EXIT => unsafe {
                VcpuContents::Exit { retcode: self.0.union.exit.retcode }
            },
            _ => panic!("unexpected VCPU packet type"),
        }
    }
}

impl PagerPacket {
    /// Returns the page request command.
    pub fn command(&self) -> sys::zx_page_request_command_t {
        self.0.command
    }

    /// Returns the range for the page request.
    pub fn range(&self) -> std::ops::Range<u64> {
        self.0.offset..self.0.offset + self.0.length
    }
}

impl InterruptPacket {
    pub fn timestamp(&self) -> sys::zx_time_t {
        self.0.timestamp
    }
}

impl PowerTransitionPacket {
    pub fn from_raw(
        packet: sys::zx_packet_processor_power_level_transition_request_t,
    ) -> PowerTransitionPacket {
        PowerTransitionPacket(packet)
    }

    pub fn domain_id(&self) -> u32 {
        self.0.domain_id
    }

    pub fn options(&self) -> u32 {
        self.0.options
    }

    pub fn control_interface(&self) -> u64 {
        self.0.control_interface
    }

    pub fn reserved(&self) -> u64 {
        self.0.reserved
    }

    pub fn control_argument(&self) -> u64 {
        self.0.control_argument
    }
}

impl Port {
    /// Create an IO port, allowing IO packets to be read and enqueued.
    ///
    /// Wraps the
    /// [zx_port_create](https://fuchsia.dev/fuchsia-src/reference/syscalls/port_create.md)
    /// syscall.
    ///
    /// # Panics
    ///
    /// If the kernel reports no memory available to create a port or the process' job policy
    /// denies port creation.
    pub fn create() -> Self {
        Self::create_with_opts(PortOptions::from_bits_truncate(0))
    }

    pub fn create_with_opts(opts: PortOptions) -> Self {
        unsafe {
            let mut handle = 0;
            let status = sys::zx_port_create(opts.bits(), &mut handle);
            ok(status).expect(
                "port creation always succeeds except with OOM or when job policy denies it",
            );
            Handle::from_raw(handle).into()
        }
    }

    /// Attempt to queue a user packet to the IO port.
    ///
    /// Wraps the
    /// [zx_port_queue](https://fuchsia.dev/fuchsia-src/reference/syscalls/port_queue.md)
    /// syscall.
    pub fn queue(&self, packet: &Packet) -> Result<(), Status> {
        let status =
            unsafe { sys::zx_port_queue(self.raw_handle(), std::ptr::from_ref(&packet.0)) };
        ok(status)
    }

    /// Wait for a packet to arrive on a (V2) port.
    ///
    /// Wraps the
    /// [zx_port_wait](https://fuchsia.dev/fuchsia-src/reference/syscalls/port_wait.md)
    /// syscall.
    pub fn wait(&self, deadline: MonotonicInstant) -> Result<Packet, Status> {
        let mut packet = Default::default();
        ok(unsafe { sys::zx_port_wait(self.raw_handle(), deadline.into_nanos(), &mut packet) })?;
        Ok(Packet(packet))
    }

    /// Cancel pending wait_async calls for an object with the given key.
    ///
    /// Wraps the
    /// [zx_port_cancel](https://fuchsia.dev/fuchsia-src/reference/syscalls/port_cancel.md)
    /// syscall.
    pub fn cancel<H>(&self, source: &H, key: u64) -> Result<(), Status>
    where
        H: AsHandleRef,
    {
        let status = unsafe { sys::zx_port_cancel(self.raw_handle(), source.raw_handle(), key) };
        ok(status)
    }
}

bitflags! {
    /// Options for wait_async
    #[repr(transparent)]
    #[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
    pub struct WaitAsyncOpts: u32 {
        /// When set, causes the system to capture a timestamp when the wait triggered.
        const TIMESTAMP = sys::ZX_WAIT_ASYNC_TIMESTAMP;
        // When set, causes the port to not enqueue a packet for signals active at
        // the time of the zx_object_wait_async() call.
        const EDGE_TRIGGERED = sys::ZX_WAIT_ASYNC_EDGE;
    }
}

#[cfg(test)]
mod tests {
    use super::*;
    use crate::{Duration, Event};
    use assert_matches::assert_matches;

    #[test]
    fn port_basic() {
        let ten_ms = Duration::from_millis(10);

        let port = Port::create();

        // Waiting now should time out.
        assert_eq!(port.wait(MonotonicInstant::after(ten_ms)), Err(Status::TIMED_OUT));

        // Send a valid packet.
        let packet = Packet::from_user_packet(42, 123, UserPacket::from_u8_array([13; 32]));
        assert!(port.queue(&packet).is_ok());

        // Waiting should succeed this time. We should get back the packet we sent.
        let read_packet = port.wait(MonotonicInstant::after(ten_ms)).unwrap();
        assert_eq!(read_packet, packet);
    }

    #[test]
    fn create_with_opts() {
        let _port = Port::create_with_opts(PortOptions::BIND_TO_INTERRUPT);
    }

    #[test]
    fn wait_async_once() {
        let ten_ms = Duration::from_millis(10);
        let key = 42;

        let port = Port::create();
        let event = Event::create();
        let no_opts = WaitAsyncOpts::empty();

        assert!(event
            .wait_async_handle(&port, key, Signals::USER_0 | Signals::USER_1, no_opts)
            .is_ok());

        // Waiting without setting any signal should time out.
        assert_eq!(port.wait(MonotonicInstant::after(ten_ms)), Err(Status::TIMED_OUT));

        // If we set a signal, we should be able to wait for it.
        assert!(event.signal_handle(Signals::NONE, Signals::USER_0).is_ok());
        let read_packet = port.wait(MonotonicInstant::after(ten_ms)).unwrap();
        assert_eq!(read_packet.key(), key);
        assert_eq!(read_packet.status(), 0);
        match read_packet.contents() {
            PacketContents::SignalOne(sig) => {
                assert_eq!(sig.trigger(), Signals::USER_0 | Signals::USER_1);
                assert_eq!(sig.observed(), Signals::USER_0);
                assert_eq!(sig.count(), 1);
            }
            _ => panic!("wrong packet type"),
        }

        // Shouldn't get any more packets.
        assert_eq!(port.wait(MonotonicInstant::after(ten_ms)), Err(Status::TIMED_OUT));

        // Calling wait_async again should result in another packet.
        assert!(event.wait_async_handle(&port, key, Signals::USER_0, no_opts).is_ok());
        let read_packet = port.wait(MonotonicInstant::after(ten_ms)).unwrap();
        assert_eq!(read_packet.key(), key);
        assert_eq!(read_packet.status(), 0);
        match read_packet.contents() {
            PacketContents::SignalOne(sig) => {
                assert_eq!(sig.trigger(), Signals::USER_0);
                assert_eq!(sig.observed(), Signals::USER_0);
                assert_eq!(sig.count(), 1);
            }
            _ => panic!("wrong packet type"),
        }

        // Calling wait_async_handle then cancel, we should not get a packet as cancel will
        // remove it from  the queue.
        assert!(event.wait_async_handle(&port, key, Signals::USER_0, no_opts).is_ok());
        assert!(port.cancel(&event, key).is_ok());
        assert_eq!(port.wait(MonotonicInstant::after(ten_ms)), Err(Status::TIMED_OUT));

        // If the event is signalled after the cancel, we also shouldn't get a packet.
        assert!(event.signal_handle(Signals::USER_0, Signals::NONE).is_ok()); // clear signal
        assert!(event.wait_async_handle(&port, key, Signals::USER_0, no_opts).is_ok());
        assert!(port.cancel(&event, key).is_ok());
        assert!(event.signal_handle(Signals::NONE, Signals::USER_0).is_ok());
        assert_eq!(port.wait(MonotonicInstant::after(ten_ms)), Err(Status::TIMED_OUT));
    }

    #[test]
    fn guest_mem_packet() {
        #[cfg(target_arch = "x86_64")]
        const GUEST_MEM_PACKET: sys::zx_packet_guest_mem_t = sys::zx_packet_guest_mem_t {
            addr: 0xaaaabbbbccccdddd,
            cr3: 0x0123456789abcdef,
            rip: 0xffffffff00000000,
            instruction_size: 8,
            default_operand_size: 2,
        };
        #[cfg(target_arch = "aarch64")]
        const GUEST_MEM_PACKET: sys::zx_packet_guest_mem_t = sys::zx_packet_guest_mem_t {
            addr: 0x8877665544332211,
            access_size: 8,
            sign_extend: true,
            xt: 0xf3,
            read: false,
            data: 0x1122334455667788,
        };
        #[cfg(target_arch = "riscv64")]
        const GUEST_MEM_PACKET: sys::zx_packet_guest_mem_t =
            sys::zx_packet_guest_mem_t { addr: 0x8877665544332211, reserved: [0; 3] };
        const KEY: u64 = 0x5555555555555555;
        const STATUS: i32 = sys::ZX_ERR_INTERNAL;

        let packet =
            Packet::from_guest_mem_packet(KEY, STATUS, GuestMemPacket::from_raw(GUEST_MEM_PACKET));

        assert_matches!(packet.contents(), PacketContents::GuestMem(GuestMemPacket(packet)) if packet == GUEST_MEM_PACKET);
        assert_eq!(packet.key(), KEY);
        assert_eq!(packet.status(), STATUS);
    }

    #[test]
    fn guest_io_packet() {
        const GUEST_IO_PACKET: sys::zx_packet_guest_io_t = sys::zx_packet_guest_io_t {
            port: 0xabcd,
            access_size: 4,
            input: true,
            data: [0xaa, 0xbb, 0xcc, 0xdd],
        };
        const KEY: u64 = 0x0123456789abcdef;
        const STATUS: i32 = sys::ZX_ERR_NO_RESOURCES;

        let packet =
            Packet::from_guest_io_packet(KEY, STATUS, GuestIoPacket::from_raw(GUEST_IO_PACKET));

        assert_matches!(packet.contents(), PacketContents::GuestIo(GuestIoPacket(packet)) if packet == GUEST_IO_PACKET);
        assert_eq!(packet.key(), KEY);
        assert_eq!(packet.status(), STATUS);
    }

    #[test]
    fn guest_vcpu_interrupt_packet() {
        // Unable to use 'const' here because we need Default::default to initialize the PadBytes.
        let guest_vcpu_packet: sys::zx_packet_guest_vcpu_t = sys::zx_packet_guest_vcpu_t {
            r#type: sys::zx_packet_guest_vcpu_type_t::ZX_PKT_GUEST_VCPU_INTERRUPT,
            union: sys::zx_packet_guest_vcpu_union_t {
                interrupt: sys::zx_packet_guest_vcpu_interrupt_t {
                    mask: 0xaaaaaaaaaaaaaaaa,
                    vector: 0x12,
                    padding1: Default::default(),
                },
            },
            padding1: Default::default(),
            reserved: 0,
        };
        const KEY: u64 = 0x0123456789abcdef;
        const STATUS: i32 = sys::ZX_ERR_NO_RESOURCES;

        let packet = Packet::from_guest_vcpu_packet(
            KEY,
            STATUS,
            GuestVcpuPacket::from_raw(guest_vcpu_packet),
        );

        assert_matches!(packet.contents(), PacketContents::GuestVcpu(GuestVcpuPacket(packet)) if packet == guest_vcpu_packet);
        assert_eq!(packet.key(), KEY);
        assert_eq!(packet.status(), STATUS);
    }

    #[test]
    fn guest_vcpu_startup_packet() {
        let guest_vcpu_packet: sys::zx_packet_guest_vcpu_t = sys::zx_packet_guest_vcpu_t {
            r#type: sys::zx_packet_guest_vcpu_type_t::ZX_PKT_GUEST_VCPU_STARTUP,
            union: sys::zx_packet_guest_vcpu_union_t {
                startup: sys::zx_packet_guest_vcpu_startup_t { id: 16, entry: 0xffffffff11111111 },
            },
            padding1: Default::default(),
            reserved: 0,
        };
        const KEY: u64 = 0x0123456789abcdef;
        const STATUS: i32 = sys::ZX_ERR_NO_RESOURCES;

        let packet = Packet::from_guest_vcpu_packet(
            KEY,
            STATUS,
            GuestVcpuPacket::from_raw(guest_vcpu_packet),
        );

        assert_matches!(packet.contents(), PacketContents::GuestVcpu(GuestVcpuPacket(packet)) if packet == guest_vcpu_packet);
        assert_eq!(packet.key(), KEY);
        assert_eq!(packet.status(), STATUS);
    }

    #[test]
    fn guest_vcpu_exit_packet() {
        let guest_vcpu_packet: sys::zx_packet_guest_vcpu_t = sys::zx_packet_guest_vcpu_t {
            r#type: sys::zx_packet_guest_vcpu_type_t::ZX_PKT_GUEST_VCPU_EXIT,
            union: sys::zx_packet_guest_vcpu_union_t {
                exit: sys::zx_packet_guest_vcpu_exit_t { retcode: 12345678, reserved: 0 },
            },
            padding1: Default::default(),
            reserved: 0,
        };
        const KEY: u64 = 0x0123456789abcdef;
        const STATUS: i32 = sys::ZX_ERR_NO_RESOURCES;

        let packet = Packet::from_guest_vcpu_packet(
            KEY,
            STATUS,
            GuestVcpuPacket::from_raw(guest_vcpu_packet),
        );

        assert_matches!(packet.contents(), PacketContents::GuestVcpu(GuestVcpuPacket(packet)) if packet == guest_vcpu_packet);
        assert_eq!(packet.key(), KEY);
        assert_eq!(packet.status(), STATUS);
    }

    #[test]
    fn power_transition_packet() {
        const POWER_TRANSITION_PACKET: sys::zx_packet_processor_power_level_transition_request_t =
            sys::zx_packet_processor_power_level_transition_request_t {
                domain_id: 0,
                options: 0,
                control_argument: 0,
                control_interface: 0,
                reserved: 0,
            };
        const KEY: u64 = 0x0123456789abcdef;
        const STATUS: i32 = sys::ZX_ERR_NO_RESOURCES;

        let packet = Packet::from_power_transition_packet(
            KEY,
            STATUS,
            PowerTransitionPacket::from_raw(POWER_TRANSITION_PACKET),
        );

        assert_matches!(
            packet.contents(),
            PacketContents::PowerTransition(PowerTransitionPacket(packet)) if packet == POWER_TRANSITION_PACKET
        );
        assert_eq!(packet.key(), KEY);
        assert_eq!(packet.status(), STATUS);
    }
}