fidl_fuchsia_test_debug__common/
fidl_fuchsia_test_debug__common.rs

1// WARNING: This file is machine generated by fidlgen.
2
3#![warn(clippy::all)]
4#![allow(unused_parens, unused_mut, unused_imports, nonstandard_style)]
5
6use bitflags::bitflags;
7use fidl::encoding::{MessageBufFor, ProxyChannelBox, ResourceDialect};
8use futures::future::{self, MaybeDone, TryFutureExt};
9use zx_status;
10
11pub mod debug_data_processor_ordinals {
12    pub const SET_DIRECTORY: u64 = 0x3010ac21cf0b4c79;
13    pub const ADD_DEBUG_VMOS: u64 = 0x48b3d3070f48199b;
14    pub const FINISH: u64 = 0x2bc6016f91bdf3a7;
15}
16
17mod internal {
18    use super::*;
19}