fidl_fuchsia_diagnostics_test__common/
fidl_fuchsia_diagnostics_test__common.rs

1// WARNING: This file is machine generated by fidlgen.
2
3#![warn(clippy::all)]
4#![allow(unused_parens, unused_mut, unused_imports, nonstandard_style)]
5
6use bitflags::bitflags;
7use fidl::encoding::{MessageBufFor, ProxyChannelBox, ResourceDialect};
8use futures::future::{self, MaybeDone, TryFutureExt};
9use zx_status;
10
11pub mod detect_controller_ordinals {
12    pub const ENTER_TEST_MODE: u64 = 0x6f4bb79cfba4f84;
13}
14
15pub mod test_case_controller_ordinals {
16    pub const RUN_DEFAULT_CYCLE: u64 = 0x6f41c0399849aea2;
17}
18
19mod internal {
20    use super::*;
21}