fidl_fuchsia_component_runner__common/
fidl_fuchsia_component_runner__common.rs

1// WARNING: This file is machine generated by fidlgen.
2
3#![warn(clippy::all)]
4#![allow(unused_parens, unused_mut, unused_imports, nonstandard_style)]
5
6use bitflags::bitflags;
7use fidl::encoding::{MessageBufFor, ProxyChannelBox, ResourceDialect};
8use futures::future::{self, MaybeDone, TryFutureExt};
9use zx_status;
10
11pub const MAX_HANDLE_COUNT: u32 = 128;
12
13pub const MAX_NAMESPACE_COUNT: u32 = 32;
14
15mod internal {
16    use super::*;
17}