fidl_fuchsia_component_runner__common/
fidl_fuchsia_component_runner__common.rs

1// WARNING: This file is machine generated by fidlgen.
2
3#![warn(clippy::all)]
4#![allow(unused_parens, unused_mut, unused_imports, nonstandard_style)]
5
6use bitflags::bitflags;
7use fidl::encoding::{MessageBufFor, ProxyChannelBox, ResourceDialect};
8use futures::future::{self, MaybeDone, TryFutureExt};
9use zx_status;
10
11pub const MAX_HANDLE_COUNT: u32 = 128;
12
13pub const MAX_NAMESPACE_COUNT: u32 = 32;
14
15pub mod component_controller_ordinals {
16    pub const STOP: u64 = 0x42ad097fa07c1b62;
17    pub const KILL: u64 = 0x3ea62e200a45aeb4;
18    pub const ON_PUBLISH_DIAGNOSTICS: u64 = 0x1f16d8c3c49c6947;
19    pub const ON_ESCROW: u64 = 0xa231349355343fc;
20    pub const ON_STOP: u64 = 0x3bfd24b031878ab2;
21}
22
23pub mod component_runner_ordinals {
24    pub const START: u64 = 0xad5a8c19f25ee09;
25}
26
27pub mod task_provider_ordinals {
28    pub const GET_JOB: u64 = 0x4c9ca4f4fdece3ad;
29}
30
31mod internal {
32    use super::*;
33}