fidl_data_zbi/
driver_config.rs

1// Copyright 2022 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// DO NOT EDIT.
6// Generated from FIDL library `zbi` by zither, a Fuchsia platform tool.
7
8#![allow(unused_imports)]
9
10use bitflags::bitflags;
11use zerocopy::{FromBytes, IntoBytes};
12
13/// ZBI_TYPE_KERNEL_DRIVER item types (for zbi_header_t.extra)
14#[repr(u32)]
15#[derive(Clone, Copy, Debug, Eq, IntoBytes, PartialEq)]
16pub enum KernelDriver {
17    /// 'PSCI'
18    ArmPsci = 0x49435350,
19
20    /// 'GIC2'
21    ArmGicV2 = 0x32434947,
22
23    /// 'GIC3'
24    ArmGicV3 = 0x33434947,
25
26    /// 'ATIM'
27    ArmGenericTimer = 0x4d495441,
28
29    /// 'ATMM'
30    ArmGenericTimerMmio = 0x4d4d5441,
31
32    /// 'PL0U'
33    Pl011Uart = 0x55304c50,
34
35    /// 'AMLU'
36    AmlogicUart = 0x554c4d41,
37
38    /// 'AMLH'
39    AmlogicHdcp = 0x484c4d41,
40
41    /// 'DW8U'
42    Dw8250Uart = 0x44573855,
43
44    /// 'RMLH' (typoed, originally intended to by 'AMLR')
45    AmlogicRngV1 = 0x484c4d52,
46
47    /// 'AMLR'
48    AmlogicRngV2 = 0x524c4d41,
49
50    /// 'WD32'
51    Generic32Watchdog = 0x32334457,
52
53    /// 'GENI'
54    GeniUart = 0x494E4547,
55
56    /// '8250'
57    I8250PioUart = 0x30353238,
58
59    /// '825M'
60    I8250Mmio32Uart = 0x4d353238,
61
62    /// '825B'
63    I8250Mmio8Uart = 0x42353238,
64
65    /// 'MMTP'
66    MotmotPower = 0x4d4d5450,
67
68    /// '370P'
69    As370Power = 0x50303733,
70
71    /// 'MNFP'
72    MoonflowerPower = 0x4d4e4650,
73
74    /// 'IMXU'
75    ImxUart = 0x55584d49,
76
77    /// 'PLIC'
78    RiscvPlic = 0x43494C50,
79
80    /// 'RTIM'
81    RiscvGenericTimer = 0x4D495452,
82
83    /// 'PXAU'
84    PxaUart = 0x50584155,
85
86    /// 'EXYU'
87    ExynosUsiUart = 0x45585955,
88}
89
90/// Kernel driver struct that can be used for simple drivers.
91/// Used by ZBI_KERNEL_DRIVER_PL011_UART, ZBI_KERNEL_DRIVER_AMLOGIC_UART, and
92/// ZBI_KERNEL_DRIVER_GENI_UART, ZBI_KERNEL_DRIVER_I8250_MMIO_UART.
93#[repr(C)]
94#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
95pub struct DcfgSimple {
96    pub mmio_phys: u64,
97    pub irq: u32,
98    pub flags: u32,
99}
100
101#[repr(C)]
102#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
103pub struct KernelDriverIrqFlags(u32);
104
105bitflags! {
106    impl KernelDriverIrqFlags : u32 {
107
108        /// When no flag is set, implies no information was obtained, and the
109        /// kernel will apply default configuration as it sees fit.
110        const EDGE_TRIGGERED = 1 << 0;
111        const LEVEL_TRIGGERED = 1 << 1;
112
113        /// Interpretation depends on whether is edge or level triggered.
114        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_LOW`.
115        /// When `EDGE_TRIGGERED` refers to `HIGH_TO_LOW`.
116        const POLARITY_LOW = 1 << 2;
117
118        /// Interpretation depends on whether is edge or level triggered.
119        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_HIGH`.
120        /// When `EDGE_TRIGGERED` refers to `LOW_TO_HIGH`.
121        const POLARITY_HIGH = 1 << 3;
122  }
123}
124
125/// Used by ZBI_KERNEL_DRIVER_I8250_PIO_UART.
126#[repr(C)]
127#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
128pub struct DcfgSimplePio {
129    pub base: u16,
130    pub reserved: u16,
131    pub irq: u32,
132}
133
134/// for ZBI_KERNEL_DRIVER_ARM_PSCI
135#[repr(C)]
136#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
137pub struct DcfgArmPsciDriver {
138    pub use_hvc: u8,
139    pub reserved: [u8; 7],
140    pub shutdown_args: [u64; 3],
141    pub reboot_args: [u64; 3],
142    pub reboot_bootloader_args: [u64; 3],
143    pub reboot_recovery_args: [u64; 3],
144}
145
146/// for ZBI_KERNEL_DRIVER_ARM_GIC_V2
147#[repr(C)]
148#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
149pub struct DcfgArmGicV2Driver {
150    pub mmio_phys: u64,
151    pub msi_frame_phys: u64,
152    pub gicd_offset: u64,
153    pub gicc_offset: u64,
154    pub gich_offset: u64,
155    pub gicv_offset: u64,
156    pub ipi_base: u32,
157    pub optional: u8,
158    pub use_msi: u8,
159    pub reserved: u16,
160}
161
162/// for ZBI_KERNEL_DRIVER_ARM_GIC_V3
163#[repr(C)]
164#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
165pub struct DcfgArmGicV3Driver {
166    pub mmio_phys: u64,
167    pub gicd_offset: u64,
168    pub gicr_offset: u64,
169    pub gicr_stride: u64,
170    pub reserved0: u64,
171    pub ipi_base: u32,
172    pub optional: u8,
173    pub reserved1: [u8; 3],
174}
175
176/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER
177#[repr(C)]
178#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
179pub struct DcfgArmGenericTimerDriver {
180    pub irq_phys: u32,
181    pub irq_virt: u32,
182    pub irq_sphys: u32,
183    pub freq_override: u32,
184}
185
186/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER_MMIO
187#[repr(C)]
188#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
189pub struct DcfgArmGenericTimerMmioDriver {
190    /// Base address of `CNTCTLBase` frame.
191    pub base_addr: u64,
192
193    /// The frequency of the main counter for the timer.
194    pub frequency: u32,
195
196    /// Bitmask containing the set of active frames.
197    pub active_frames_mask: u8,
198    pub reserved0: [u8; 3],
199
200    /// Information for each individual frame.
201    /// Inactive frames must be zero-filled.
202    pub frames: [DcfgSimple; 8],
203}
204
205/// for ZBI_KERNEL_DRIVER_AMLOGIC_HDCP
206#[repr(C)]
207#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
208pub struct DcfgAmlogicHdcpDriver {
209    pub preset_phys: u64,
210    pub hiu_phys: u64,
211    pub hdmitx_phys: u64,
212}
213
214/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V1
215/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V2
216#[repr(C)]
217#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
218pub struct DcfgAmlogicRngDriver {
219    pub rng_data_phys: u64,
220    pub rng_status_phys: u64,
221    pub rng_refresh_interval_usec: u64,
222}
223
224/// Defines a register write action for a generic kernel watchdog driver.  An
225/// action consists of the following steps.
226///
227/// 1) Read from the register located a physical address |addr|
228/// 2) Clear all of the bits in the value which was read using the |clr_mask|
229/// 3) Set all of the bits in the value using the |set_mask|
230/// 4) Write this value back to the address located at addr
231#[repr(C)]
232#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
233pub struct DcfgGeneric32WatchdogAction {
234    pub addr: u64,
235    pub clr_mask: u32,
236    pub set_mask: u32,
237}
238
239#[repr(C)]
240#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
241pub struct KernelDriverGeneric32WatchdogFlags(u32);
242
243bitflags! {
244    impl KernelDriverGeneric32WatchdogFlags : u32 {
245        const ENABLED = 1 << 0;
246  }
247}
248
249/// 1ms
250pub const KERNEL_DRIVER_GENERIC32_WATCHDOG_MIN_PERIOD: i64 = 1000000;
251
252/// Definitions of actions which may be taken by a generic 32 bit watchdog timer
253/// kernel driver which may be passed by a bootloader.  Field definitions are as
254/// follows.
255#[repr(C)]
256#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
257pub struct DcfgGeneric32Watchdog {
258    /// The address and masks needed to "pet" (aka, dismiss) a hardware watchdog timer.
259    pub pet_action: DcfgGeneric32WatchdogAction,
260
261    /// The address and masks needed to enable a hardware watchdog timer.  If enable
262    /// is an unsupported operation, the addr of the |enable_action| shall be zero.
263    pub enable_action: DcfgGeneric32WatchdogAction,
264
265    /// The address and masks needed to disable a hardware watchdog timer.  If
266    /// disable is an unsupported operation, the addr of the |disable_action| shall
267    /// be zero.
268    pub disable_action: DcfgGeneric32WatchdogAction,
269
270    /// The period of the watchdog timer given in nanoseconds.  When enabled, the
271    /// watchdog timer driver must pet the watch dog at least this often.  The value
272    /// must be at least 1 mSec, typically much larger (on the order of a second or
273    /// two).
274    pub watchdog_period_nsec: i64,
275
276    /// Storage for additional flags.  Currently, only one flag is defined,
277    /// "FLAG_ENABLED".  When this flag is set, it indicates that the watchdog timer
278    /// was left enabled by the bootloader at startup.
279    pub flags: KernelDriverGeneric32WatchdogFlags,
280    pub reserved: u32,
281}
282
283/// for ZBI_KERNEL_DRIVER_RISCV_PLIC
284#[repr(C)]
285#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
286pub struct DcfgRiscvPlicDriver {
287    pub mmio_phys: u64,
288    pub num_irqs: u32,
289    pub reserved: u32,
290}
291
292/// for ZBI_KERNEL_DRIVER_RISCV_GENERIC_TIMER
293#[repr(C)]
294#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
295pub struct DcfgRiscvGenericTimerDriver {
296    pub freq_hz: u32,
297    pub reserved: u32,
298}
fidl_data_zbi/driver_config.rs

fidl_data_zbi/
driver_config.rs
