fidl_data_zbi/
driver_config.rs

1// Copyright 2022 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// DO NOT EDIT.
6// Generated from FIDL library `zbi` by zither, a Fuchsia platform tool.
7
8#![allow(unused_imports)]
9
10use bitflags::bitflags;
11use zerocopy::{FromBytes, IntoBytes};
12
13/// ZBI_TYPE_KERNEL_DRIVER item types (for zbi_header_t.extra)
14#[repr(u32)]
15#[derive(Clone, Copy, Debug, Eq, IntoBytes, PartialEq)]
16pub enum KernelDriver {
17    /// 'PSCI'
18    ArmPsci = 0x49435350,
19
20    /// 'PSCS'
21    ArmPsciCpuSuspend = 0x53435350,
22
23    /// 'GIC2'
24    ArmGicV2 = 0x32434947,
25
26    /// 'GIC3'
27    ArmGicV3 = 0x33434947,
28
29    /// 'ATIM'
30    ArmGenericTimer = 0x4d495441,
31
32    /// 'ATMM'
33    ArmGenericTimerMmio = 0x4d4d5441,
34
35    /// 'PL0U'
36    Pl011Uart = 0x55304c50,
37
38    /// 'AMLU'
39    AmlogicUart = 0x554c4d41,
40
41    /// 'AMLH'
42    AmlogicHdcp = 0x484c4d41,
43
44    /// 'DW8U'
45    Dw8250Uart = 0x44573855,
46
47    /// 'RMLH' (typoed, originally intended to by 'AMLR')
48    AmlogicRngV1 = 0x484c4d52,
49
50    /// 'AMLR'
51    AmlogicRngV2 = 0x524c4d41,
52
53    /// 'WD32'
54    Generic32Watchdog = 0x32334457,
55
56    /// 'GENI'
57    GeniUart = 0x494E4547,
58
59    /// '8250'
60    I8250PioUart = 0x30353238,
61
62    /// '825M'
63    I8250Mmio32Uart = 0x4d353238,
64
65    /// '825B'
66    I8250Mmio8Uart = 0x42353238,
67
68    /// 'MMTP'
69    MotmotPower = 0x4d4d5450,
70
71    /// '370P'
72    As370Power = 0x50303733,
73
74    /// 'MNFP'
75    MoonflowerPower = 0x4d4e4650,
76
77    /// 'IMXU'
78    ImxUart = 0x55584d49,
79
80    /// 'PLIC'
81    RiscvPlic = 0x43494C50,
82
83    /// 'RTIM'
84    RiscvGenericTimer = 0x4D495452,
85
86    /// 'PXAU'
87    PxaUart = 0x50584155,
88
89    /// 'EXYU'
90    ExynosUsiUart = 0x45585955,
91}
92
93/// Kernel driver struct that can be used for simple drivers.
94/// Used by ZBI_KERNEL_DRIVER_PL011_UART, ZBI_KERNEL_DRIVER_AMLOGIC_UART, and
95/// ZBI_KERNEL_DRIVER_GENI_UART, ZBI_KERNEL_DRIVER_I8250_MMIO_UART.
96#[repr(C)]
97#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
98pub struct DcfgSimple {
99    pub mmio_phys: u64,
100    pub irq: u32,
101    pub flags: u32,
102}
103
104#[repr(C)]
105#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
106pub struct KernelDriverIrqFlags(u32);
107
108bitflags! {
109    impl KernelDriverIrqFlags : u32 {
110
111        /// When no flag is set, implies no information was obtained, and the
112        /// kernel will apply default configuration as it sees fit.
113        const EDGE_TRIGGERED = 1 << 0;
114        const LEVEL_TRIGGERED = 1 << 1;
115
116        /// Interpretation depends on whether is edge or level triggered.
117        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_LOW`.
118        /// When `EDGE_TRIGGERED` refers to `HIGH_TO_LOW`.
119        const POLARITY_LOW = 1 << 2;
120
121        /// Interpretation depends on whether is edge or level triggered.
122        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_HIGH`.
123        /// When `EDGE_TRIGGERED` refers to `LOW_TO_HIGH`.
124        const POLARITY_HIGH = 1 << 3;
125  }
126}
127
128/// Used by ZBI_KERNEL_DRIVER_I8250_PIO_UART.
129#[repr(C)]
130#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
131pub struct DcfgSimplePio {
132    pub base: u16,
133    pub reserved: u16,
134    pub irq: u32,
135}
136
137/// for ZBI_KERNEL_DRIVER_ARM_PSCI
138#[repr(C)]
139#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
140pub struct DcfgArmPsciDriver {
141    pub use_hvc: u8,
142    pub reserved: [u8; 7],
143    pub shutdown_args: [u64; 3],
144    pub reboot_args: [u64; 3],
145    pub reboot_bootloader_args: [u64; 3],
146    pub reboot_recovery_args: [u64; 3],
147}
148
149/// for ZBI_KERNEL_DRIVER_ARM_GIC_V2
150#[repr(C)]
151#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
152pub struct DcfgArmGicV2Driver {
153    pub mmio_phys: u64,
154    pub msi_frame_phys: u64,
155    pub gicd_offset: u64,
156    pub gicc_offset: u64,
157    pub gich_offset: u64,
158    pub gicv_offset: u64,
159    pub ipi_base: u32,
160    pub optional: u8,
161    pub use_msi: u8,
162    pub reserved: u16,
163}
164
165/// for ZBI_KERNEL_DRIVER_ARM_GIC_V3
166#[repr(C)]
167#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
168pub struct DcfgArmGicV3Driver {
169    pub mmio_phys: u64,
170    pub gicd_offset: u64,
171    pub gicr_offset: u64,
172    pub gicr_stride: u64,
173    pub reserved0: u64,
174    pub ipi_base: u32,
175    pub optional: u8,
176    pub reserved1: [u8; 3],
177}
178
179/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER
180#[repr(C)]
181#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
182pub struct DcfgArmGenericTimerDriver {
183    pub irq_phys: u32,
184    pub irq_virt: u32,
185    pub irq_sphys: u32,
186    pub freq_override: u32,
187}
188
189#[repr(C)]
190#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
191pub struct DcfgArmGenericTimerMmioFrame {
192    /// Base address for the frame's EL1 view.
193    pub mmio_phys_el1: u64,
194
195    /// Base address for the frame's EL0 view.
196    /// This is optional.
197    pub mmio_phys_el0: u64,
198
199    /// IRQ information for physical timer. This is mandatory.
200    pub irq_phys: u32,
201
202    /// Same scheme as `DcfgSimple::irq`. This is mandatory.
203    pub irq_phys_flags: u32,
204
205    /// IRQ information for virtual timer.
206    /// This is optional.
207    /// When is not present both `irq_virt` and `irq_virt_flags` will be zero.
208    pub irq_virt: u32,
209
210    /// Same scheme as `DcfgSimple::irq`.
211    pub irq_virt_flags: u32,
212}
213
214/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER_MMIO
215#[repr(C)]
216#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
217pub struct DcfgArmGenericTimerMmioDriver {
218    /// Base address of `CNTCTLBase` frame.
219    pub mmio_phys: u64,
220
221    /// The frequency of the main counter for the timer.
222    pub frequency: u32,
223
224    /// Bitmask containing the set of active frames.
225    /// The `i-th` frame is considered active iff the `i`-th bit is set.
226    /// Note: While there may be up to 8 frames, both missing and disabled frames are treated
227    /// as inactive. Disabled frame information will be present, while missing frames will be zeroed.
228    pub active_frames_mask: u8,
229    pub reserved0: [u8; 3],
230
231    /// Information for each individual frame.
232    /// Inactive frames must be zero-filled.
233    pub frames: [DcfgArmGenericTimerMmioFrame; 8],
234}
235
236/// for ZBI_KERNEL_DRIVER_AMLOGIC_HDCP
237#[repr(C)]
238#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
239pub struct DcfgAmlogicHdcpDriver {
240    pub preset_phys: u64,
241    pub hiu_phys: u64,
242    pub hdmitx_phys: u64,
243}
244
245/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V1
246/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V2
247#[repr(C)]
248#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
249pub struct DcfgAmlogicRngDriver {
250    pub rng_data_phys: u64,
251    pub rng_status_phys: u64,
252    pub rng_refresh_interval_usec: u64,
253}
254
255/// Defines a register write action for a generic kernel watchdog driver.  An
256/// action consists of the following steps.
257///
258/// 1) Read from the register located a physical address |addr|
259/// 2) Clear all of the bits in the value which was read using the |clr_mask|
260/// 3) Set all of the bits in the value using the |set_mask|
261/// 4) Write this value back to the address located at addr
262#[repr(C)]
263#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
264pub struct DcfgGeneric32WatchdogAction {
265    pub addr: u64,
266    pub clr_mask: u32,
267    pub set_mask: u32,
268}
269
270#[repr(C)]
271#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
272pub struct KernelDriverGeneric32WatchdogFlags(u32);
273
274bitflags! {
275    impl KernelDriverGeneric32WatchdogFlags : u32 {
276        const ENABLED = 1 << 0;
277  }
278}
279
280/// 1ms
281pub const KERNEL_DRIVER_GENERIC32_WATCHDOG_MIN_PERIOD: i64 = 1000000;
282
283/// Definitions of actions which may be taken by a generic 32 bit watchdog timer
284/// kernel driver which may be passed by a bootloader.  Field definitions are as
285/// follows.
286#[repr(C)]
287#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
288pub struct DcfgGeneric32Watchdog {
289    /// The address and masks needed to "pet" (aka, dismiss) a hardware watchdog timer.
290    pub pet_action: DcfgGeneric32WatchdogAction,
291
292    /// The address and masks needed to enable a hardware watchdog timer.  If enable
293    /// is an unsupported operation, the addr of the |enable_action| shall be zero.
294    pub enable_action: DcfgGeneric32WatchdogAction,
295
296    /// The address and masks needed to disable a hardware watchdog timer.  If
297    /// disable is an unsupported operation, the addr of the |disable_action| shall
298    /// be zero.
299    pub disable_action: DcfgGeneric32WatchdogAction,
300
301    /// The period of the watchdog timer given in nanoseconds.  When enabled, the
302    /// watchdog timer driver must pet the watch dog at least this often.  The value
303    /// must be at least 1 mSec, typically much larger (on the order of a second or
304    /// two).
305    pub watchdog_period_nsec: i64,
306
307    /// Storage for additional flags.  Currently, only one flag is defined,
308    /// "FLAG_ENABLED".  When this flag is set, it indicates that the watchdog timer
309    /// was left enabled by the bootloader at startup.
310    pub flags: KernelDriverGeneric32WatchdogFlags,
311    pub reserved: u32,
312}
313
314/// for ZBI_KERNEL_DRIVER_RISCV_PLIC
315#[repr(C)]
316#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
317pub struct DcfgRiscvPlicDriver {
318    pub mmio_phys: u64,
319    pub num_irqs: u32,
320    pub reserved: u32,
321}
322
323/// for ZBI_KERNEL_DRIVER_RISCV_GENERIC_TIMER
324#[repr(C)]
325#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
326pub struct DcfgRiscvGenericTimerDriver {
327    pub freq_hz: u32,
328    pub reserved: u32,
329}
330
331#[repr(C)]
332#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
333pub struct ArmPsciCpuSuspendStateFlags(u32);
334
335bitflags! {
336    impl ArmPsciCpuSuspendStateFlags : u32 {
337
338        /// If set, when entering the associated low power state the CPU's architectural timer will be
339        /// turned off, making it an unsuitable source for exiting the low power state.
340        /// A different source must be programmed.
341        const LOCAL_TIMER_STOPS = 1 << 0;
342
343        /// If set, the PSCI CPU Suspend operation will affect the entire power domain, implying all other
344        /// CPUs of the power domain must be in a low power mode. That is, the last CPU in the power
345        /// domain is the one to enter this power state.
346        const TARGETS_POWER_DOMAIN = 1 << 1;
347  }
348}
349
350/// The ZBI_KERNEL_DRIVER_ARM_PSCI_CPU_SUSPEND's payload consists on any number of
351/// `DcfgArmPsciCpuSuspendState` entries.
352///
353/// The length of the item is `sizeof(zbi_dcfg_arm_psci_cou_suspend_state_t)` times the number of
354/// entries. Each entry describes an 'idle state' that can be entered through PSCI CPU Suspend call.
355///
356/// Entries in the table may be in any order, and only a single item of type
357/// ZBI_KERNEL_DRIVER_ARM_PSCI_CPU_SUSPEND should be present in the ZBI.
358#[repr(C)]
359#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
360pub struct DcfgArmPsciCpuSuspendState {
361    /// Unique identifier representing this suspend state.
362    pub id: u32,
363
364    /// PSCI power_state as described in "Section 5.4.2. of Arm Power State Coordination Interface"
365    /// v1.3.
366    pub power_state: u32,
367    pub flags: ArmPsciCpuSuspendStateFlags,
368
369    /// Latency in microseconds to enter the low power state.
370    pub entry_latency_us: u32,
371
372    /// Latency in microseconds to exit the low power state.
373    pub exit_latency_us: u32,
374
375    /// Minimum time in microseconds, including `entry_latency`, to stay in this low power state.
376    /// Spending less time would be inefficient energy-wise.
377    pub min_residency_us: u32,
378}
fidl_data_zbi/driver_config.rs

fidl_data_zbi/
driver_config.rs
