fidl_data_zbi/
driver_config.rs

1// Copyright 2022 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// DO NOT EDIT.
6// Generated from FIDL library `zbi` by zither, a Fuchsia platform tool.
7
8#![allow(unused_imports)]
9
10use bitflags::bitflags;
11use zerocopy::{FromBytes, IntoBytes};
12
13/// ZBI_TYPE_KERNEL_DRIVER item types (for zbi_header_t.extra)
14#[repr(u32)]
15#[derive(Clone, Copy, Debug, Eq, IntoBytes, PartialEq)]
16pub enum KernelDriver {
17    /// 'PSCI'
18    ArmPsci = 0x49435350,
19
20    /// 'PSCS'
21    ArmPsciCpuSuspend = 0x53435350,
22
23    /// 'GIC2'
24    ArmGicV2 = 0x32434947,
25
26    /// 'GIC3'
27    ArmGicV3 = 0x33434947,
28
29    /// 'ATIM'
30    ArmGenericTimer = 0x4d495441,
31
32    /// 'ATMM'
33    ArmGenericTimerMmio = 0x4d4d5441,
34
35    /// 'PL0U'
36    Pl011Uart = 0x55304c50,
37
38    /// 'AMLU'
39    AmlogicUart = 0x554c4d41,
40
41    /// 'AMLH'
42    AmlogicHdcp = 0x484c4d41,
43
44    /// 'DW8U'
45    Dw8250Uart = 0x44573855,
46
47    /// 'RMLH' (typoed, originally intended to by 'AMLR')
48    AmlogicRng = 0x484c4d52,
49
50    /// 'WD32'
51    Generic32Watchdog = 0x32334457,
52
53    /// 'GENI'
54    GeniUart = 0x494E4547,
55
56    /// '8250'
57    I8250PioUart = 0x30353238,
58
59    /// '825M'
60    I8250Mmio32Uart = 0x4d353238,
61
62    /// '825B'
63    I8250Mmio8Uart = 0x42353238,
64
65    /// 'MMTP'
66    MotmotPower = 0x4d4d5450,
67
68    /// '370P'
69    As370Power = 0x50303733,
70
71    /// 'MNFP'
72    MoonflowerPower = 0x4d4e4650,
73
74    /// 'IRSP'
75    IrisPower = 0x49525350,
76
77    /// 'IMXU'
78    ImxUart = 0x55584d49,
79
80    /// 'PLIC'
81    RiscvPlic = 0x43494C50,
82
83    /// 'RTIM'
84    RiscvGenericTimer = 0x4D495452,
85
86    /// 'PXAU'
87    PxaUart = 0x50584155,
88
89    /// 'EXYU'
90    ExynosUsiUart = 0x45585955,
91
92    /// `QRNG`
93    QcomRng = 0x474E5251,
94
95    /// 'SMMU'
96    ArmSmmu = 0x554D4D51,
97}
98
99impl KernelDriver {
100    pub fn from_raw(raw: u32) -> Option<Self> {
101        match raw {
102            0x49435350 => Some(Self::ArmPsci),
103
104            0x53435350 => Some(Self::ArmPsciCpuSuspend),
105
106            0x32434947 => Some(Self::ArmGicV2),
107
108            0x33434947 => Some(Self::ArmGicV3),
109
110            0x4d495441 => Some(Self::ArmGenericTimer),
111
112            0x4d4d5441 => Some(Self::ArmGenericTimerMmio),
113
114            0x55304c50 => Some(Self::Pl011Uart),
115
116            0x554c4d41 => Some(Self::AmlogicUart),
117
118            0x484c4d41 => Some(Self::AmlogicHdcp),
119
120            0x44573855 => Some(Self::Dw8250Uart),
121
122            0x484c4d52 => Some(Self::AmlogicRng),
123
124            0x32334457 => Some(Self::Generic32Watchdog),
125
126            0x494E4547 => Some(Self::GeniUart),
127
128            0x30353238 => Some(Self::I8250PioUart),
129
130            0x4d353238 => Some(Self::I8250Mmio32Uart),
131
132            0x42353238 => Some(Self::I8250Mmio8Uart),
133
134            0x4d4d5450 => Some(Self::MotmotPower),
135
136            0x50303733 => Some(Self::As370Power),
137
138            0x4d4e4650 => Some(Self::MoonflowerPower),
139
140            0x49525350 => Some(Self::IrisPower),
141
142            0x55584d49 => Some(Self::ImxUart),
143
144            0x43494C50 => Some(Self::RiscvPlic),
145
146            0x4D495452 => Some(Self::RiscvGenericTimer),
147
148            0x50584155 => Some(Self::PxaUart),
149
150            0x45585955 => Some(Self::ExynosUsiUart),
151
152            0x474E5251 => Some(Self::QcomRng),
153
154            0x554D4D51 => Some(Self::ArmSmmu),
155
156            _ => None,
157        }
158    }
159}
160
161/// Kernel driver struct that can be used for simple drivers.
162/// Used by ZBI_KERNEL_DRIVER_PL011_UART, ZBI_KERNEL_DRIVER_AMLOGIC_UART, and
163/// ZBI_KERNEL_DRIVER_GENI_UART, ZBI_KERNEL_DRIVER_I8250_MMIO_UART.
164#[repr(C)]
165#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
166pub struct DcfgSimple {
167    pub mmio_phys: u64,
168    pub irq: u32,
169    pub flags: u32,
170}
171
172#[repr(C)]
173#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
174pub struct KernelDriverIrqFlags(u32);
175
176bitflags::bitflags! {
177    impl KernelDriverIrqFlags : u32 {
178
179        /// When no flag is set, implies no information was obtained, and the
180        /// kernel will apply default configuration as it sees fit.
181        const EDGE_TRIGGERED = 1 << 0;
182        const LEVEL_TRIGGERED = 1 << 1;
183
184        /// Interpretation depends on whether is edge or level triggered.
185        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_LOW`.
186        /// When `EDGE_TRIGGERED` refers to `HIGH_TO_LOW`.
187        const POLARITY_LOW = 1 << 2;
188
189        /// Interpretation depends on whether is edge or level triggered.
190        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_HIGH`.
191        /// When `EDGE_TRIGGERED` refers to `LOW_TO_HIGH`.
192        const POLARITY_HIGH = 1 << 3;
193  }
194}
195
196/// Used by ZBI_KERNEL_DRIVER_I8250_PIO_UART.
197#[repr(C)]
198#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
199pub struct DcfgSimplePio {
200    pub base: u16,
201    pub reserved: u16,
202    pub irq: u32,
203}
204
205/// for ZBI_KERNEL_DRIVER_ARM_PSCI
206#[repr(C)]
207#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
208pub struct DcfgArmPsciDriver {
209    pub use_hvc: u8,
210    pub reserved: [u8; 7],
211    pub shutdown_args: [u64; 3],
212    pub reboot_args: [u64; 3],
213    pub reboot_bootloader_args: [u64; 3],
214    pub reboot_recovery_args: [u64; 3],
215}
216
217/// for ZBI_KERNEL_DRIVER_ARM_GIC_V2
218#[repr(C)]
219#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
220pub struct DcfgArmGicV2Driver {
221    pub mmio_phys: u64,
222    pub msi_frame_phys: u64,
223    pub gicd_offset: u64,
224    pub gicc_offset: u64,
225    pub gich_offset: u64,
226    pub gicv_offset: u64,
227    pub ipi_base: u32,
228    pub optional: u8,
229    pub use_msi: u8,
230    pub reserved: u16,
231}
232
233/// for ZBI_KERNEL_DRIVER_ARM_GIC_V3
234#[repr(C)]
235#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
236pub struct DcfgArmGicV3Driver {
237    pub mmio_phys: u64,
238    pub gicd_offset: u64,
239    pub gicr_offset: u64,
240    pub gicr_stride: u64,
241    pub reserved0: u64,
242    pub ipi_base: u32,
243    pub optional: u8,
244    pub reserved1: [u8; 3],
245}
246
247/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER
248#[repr(C)]
249#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
250pub struct DcfgArmGenericTimerDriver {
251    pub irq_phys: u32,
252    pub irq_virt: u32,
253    pub irq_sphys: u32,
254    pub freq_override: u32,
255}
256
257#[repr(C)]
258#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
259pub struct DcfgArmGenericTimerMmioFrame {
260    /// Base address for the frame's EL1 view.
261    pub mmio_phys_el1: u64,
262
263    /// Base address for the frame's EL0 view.
264    /// This is optional.
265    pub mmio_phys_el0: u64,
266
267    /// IRQ information for physical timer. This is mandatory.
268    pub irq_phys: u32,
269
270    /// Same scheme as `DcfgSimple::irq`. This is mandatory.
271    pub irq_phys_flags: u32,
272
273    /// IRQ information for virtual timer.
274    /// This is optional.
275    /// When is not present both `irq_virt` and `irq_virt_flags` will be zero.
276    pub irq_virt: u32,
277
278    /// Same scheme as `DcfgSimple::irq`.
279    pub irq_virt_flags: u32,
280}
281
282/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER_MMIO
283#[repr(C)]
284#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
285pub struct DcfgArmGenericTimerMmioDriver {
286    /// Base address of `CNTCTLBase` frame.
287    pub mmio_phys: u64,
288
289    /// The frequency of the main counter for the timer.
290    pub frequency: u32,
291
292    /// Bitmask containing the set of active frames.
293    /// The `i-th` frame is considered active iff the `i`-th bit is set.
294    /// Note: While there may be up to 8 frames, both missing and disabled frames are treated
295    /// as inactive. Disabled frame information will be present, while missing frames will be zeroed.
296    pub active_frames_mask: u8,
297    pub reserved0: [u8; 3],
298
299    /// Information for each individual frame.
300    /// Inactive frames must be zero-filled.
301    pub frames: [DcfgArmGenericTimerMmioFrame; 8],
302}
303
304/// for ZBI_KERNEL_DRIVER_AMLOGIC_HDCP
305#[repr(C)]
306#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
307pub struct DcfgAmlogicHdcpDriver {
308    pub preset_phys: u64,
309    pub hiu_phys: u64,
310    pub hdmitx_phys: u64,
311}
312
313/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG
314#[repr(C)]
315#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
316pub struct DcfgAmlogicRngDriver {
317    pub rng_data_phys: u64,
318    pub rng_status_phys: u64,
319    pub rng_refresh_interval_usec: u64,
320}
321
322/// Defines a register write action for a generic kernel watchdog driver.  An
323/// action consists of the following steps.
324///
325/// 1) Read from the register located a physical address |addr|
326/// 2) Clear all of the bits in the value which was read using the |clr_mask|
327/// 3) Set all of the bits in the value using the |set_mask|
328/// 4) Write this value back to the address located at addr
329#[repr(C)]
330#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
331pub struct DcfgGeneric32WatchdogAction {
332    pub addr: u64,
333    pub clr_mask: u32,
334    pub set_mask: u32,
335}
336
337#[repr(C)]
338#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
339pub struct KernelDriverGeneric32WatchdogFlags(u32);
340
341bitflags::bitflags! {
342    impl KernelDriverGeneric32WatchdogFlags : u32 {
343        const ENABLED = 1 << 0;
344  }
345}
346
347/// 1ms
348pub const KERNEL_DRIVER_GENERIC32_WATCHDOG_MIN_PERIOD: i64 = 1000000;
349
350/// Definitions of actions which may be taken by a generic 32 bit watchdog timer
351/// kernel driver which may be passed by a bootloader.  Field definitions are as
352/// follows.
353#[repr(C)]
354#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
355pub struct DcfgGeneric32Watchdog {
356    /// The address and masks needed to "pet" (aka, dismiss) a hardware watchdog timer.
357    pub pet_action: DcfgGeneric32WatchdogAction,
358
359    /// The address and masks needed to enable a hardware watchdog timer.  If enable
360    /// is an unsupported operation, the addr of the |enable_action| shall be zero.
361    pub enable_action: DcfgGeneric32WatchdogAction,
362
363    /// The address and masks needed to disable a hardware watchdog timer.  If
364    /// disable is an unsupported operation, the addr of the |disable_action| shall
365    /// be zero.
366    pub disable_action: DcfgGeneric32WatchdogAction,
367
368    /// The period of the watchdog timer given in nanoseconds.  When enabled, the
369    /// watchdog timer driver must pet the watch dog at least this often.  The value
370    /// must be at least 1 mSec, typically much larger (on the order of a second or
371    /// two).
372    pub watchdog_period_nsec: i64,
373
374    /// Storage for additional flags.  Currently, only one flag is defined,
375    /// "FLAG_ENABLED".  When this flag is set, it indicates that the watchdog timer
376    /// was left enabled by the bootloader at startup.
377    pub flags: KernelDriverGeneric32WatchdogFlags,
378    pub reserved: u32,
379}
380
381/// for ZBI_KERNEL_DRIVER_RISCV_PLIC
382#[repr(C)]
383#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
384pub struct DcfgRiscvPlicDriver {
385    /// Physical address of the PLIC MMIO region.
386    pub mmio_phys: u64,
387
388    /// Size in bytes of the PLIC MMIO region.
389    pub size_bytes: u32,
390
391    /// Number of supported IRQs.
392    pub num_irqs: u32,
393}
394
395/// for ZBI_KERNEL_DRIVER_RISCV_GENERIC_TIMER
396#[repr(C)]
397#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
398pub struct DcfgRiscvGenericTimerDriver {
399    pub freq_hz: u32,
400    pub reserved: u32,
401}
402
403#[repr(C)]
404#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
405pub struct ArmPsciCpuSuspendStateFlags(u32);
406
407bitflags::bitflags! {
408    impl ArmPsciCpuSuspendStateFlags : u32 {
409
410        /// If set, when entering the associated low power state the CPU's architectural timer will be
411        /// turned off, making it an unsuitable source for exiting the low power state.
412        /// A different source must be programmed.
413        const LOCAL_TIMER_STOPS = 1 << 0;
414
415        /// If set, the PSCI CPU Suspend operation will affect the entire power domain, implying all other
416        /// CPUs of the power domain must be in a low power mode. That is, the last CPU in the power
417        /// domain is the one to enter this power state.
418        const TARGETS_POWER_DOMAIN = 1 << 1;
419  }
420}
421
422/// The ZBI_KERNEL_DRIVER_ARM_PSCI_CPU_SUSPEND's payload consists on any number of
423/// `DcfgArmPsciCpuSuspendState` entries.
424///
425/// The length of the item is `sizeof(zbi_dcfg_arm_psci_cou_suspend_state_t)` times the number of
426/// entries. Each entry describes an 'idle state' that can be entered through PSCI CPU Suspend call.
427///
428/// Entries in the table may be in any order, and only a single item of type
429/// ZBI_KERNEL_DRIVER_ARM_PSCI_CPU_SUSPEND should be present in the ZBI.
430#[repr(C)]
431#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
432pub struct DcfgArmPsciCpuSuspendState {
433    /// Unique identifier representing this suspend state.
434    pub id: u32,
435
436    /// PSCI power_state as described in "Section 5.4.2. of Arm Power State Coordination Interface"
437    /// v1.3.
438    pub power_state: u32,
439    pub flags: ArmPsciCpuSuspendStateFlags,
440
441    /// Latency in microseconds to enter the low power state.
442    pub entry_latency_us: u32,
443
444    /// Latency in microseconds to exit the low power state.
445    pub exit_latency_us: u32,
446
447    /// Minimum time in microseconds, including `entry_latency`, to stay in this low power state.
448    /// Spending less time would be inefficient energy-wise.
449    pub min_residency_us: u32,
450}
451
452#[repr(C)]
453#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
454pub struct QcomRngFlags(u32);
455
456bitflags::bitflags! {
457    impl QcomRngFlags : u32 {
458
459        /// The driver has been handed off, configured and initialized.
460        const ENABLED = 1 << 0;
461  }
462}
463
464#[repr(C)]
465#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
466pub struct DcfgQcomRng {
467    /// Base address of the register banks for the device.
468    pub mmio_phys: u64,
469    pub flags: QcomRngFlags,
470    pub reserved: [u8; 4],
471}
472
473pub const KERNEL_DRIVER_SMMU_MAX_IRQS: u32 = 128;
474
475pub const KERNEL_DRIVER_SMMU_MAX_HANDOFF_SMRS: u32 = 16;
476
477/// The IRQ flags as they would be reported by a device tree description.
478#[repr(C)]
479#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
480pub struct ArmSmmuIrqFlags(u32);
481
482bitflags::bitflags! {
483    impl ArmSmmuIrqFlags : u32 {
484
485        /// A rising edge triggered interrupt.
486        const RISING_EDGE = 1 << 0;
487
488        /// A falling edge triggered interrupt.
489        const FALLING_EDGE = 1 << 1;
490
491        /// An active high level triggered interrupt.
492        const ACTIVE_HIGH = 1 << 2;
493
494        /// An active low level triggered interrupt.
495        const ACTIVE_LOW = 1 << 3;
496  }
497}
498
499#[repr(C)]
500#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
501pub struct DcfgArmSmmuIrq {
502    /// The IRQ number reported as an "absolute" GIC interrupt index.  SMMU
503    /// interrupts are expected to be SPIs, and the SPI range of a GIC's
504    /// interrupt indices starts at 32.  Because of this, it can be assumed that
505    /// any interrupt number which is < 32 indicates an invalid interrupt.
506    pub num: u32,
507
508    /// The IRQ flags as they would be reported by a device tree description.
509    pub flags: ArmSmmuIrqFlags,
510}
511
512#[repr(C)]
513#[derive(Clone, Copy, Debug, Eq, PartialEq)]
514pub struct DcfgArmSmmuDriver {
515    /// Base physical address of the SMMU address space.  This is also the start of
516    /// Global Register Space 0 in the SMMU.  The effective size of these registers
517    /// will be determined at runtime from the ID registers present in this first
518    /// page, specifically the number of context banks in IDR1.NUMCB.
519    ///
520    /// See:
521    ///
522    /// ARM System Memory Management Unit Architecture Specification
523    /// SMMU architecture version 2.0
524    /// ARM IHI 0062D.c
525    ///
526    /// for more details.
527    pub mmio_phys: u64,
528
529    /// The number of context banks that a driver should limit itself to using,
530    /// or 0 if all discovered context banks are available for use.
531    pub num_context_banks_override: u32,
532
533    /// The number of stream match registers that a driver should limit itself
534    /// to using, or 0 if all discovered SMRs are available for use.
535    pub num_smr_override: u32,
536
537    /// An array of context bank interrupt definitions discovered during device
538    /// enumeration.  |irq_cnt| reports the total number of valid members while
539    /// |irqs|, while |global_irq_cnt| reports the total number of global
540    /// interrupts in |irqs|, with the rest of the interrupts being context bank
541    /// interrupts.  So:
542    ///
543    /// + IRQs [0, global_irq_cnt) are global interrupts
544    /// + IRQs [global_irq_cnt, irq_cnt) are context bank interrupts
545    ///   corresponding to context banks [0, irq_cnt - global_irq_cnt)
546    pub irq_cnt: u32,
547    pub global_irq_cnt: u32,
548    pub irqs: [DcfgArmSmmuIrq; 128],
549
550    /// An array of stream IDs (defined using SMR value/mask encoding) which are
551    /// being "handed off" from the bootloader to the HLOS.  Downstream drivers
552    /// should take care to preserve the existing configuration for these stream
553    /// ids.  |handoff_smr_cnt| reports the number of members of |handoff_smrs|
554    /// which are valid.
555    ///
556    /// Note:  Stream ID ranges in SMRs are encoded using two 16 bit fields, a
557    /// value field and a mask field.  These two fields are packed into a single
558    /// 32-bit integer, with the mask packed into the upper 16 bits, and the
559    /// value packed into the lower 16 bits.
560    pub handoff_smr_cnt: u32,
561    pub handoff_smrs: [u32; 16],
562}
fidl_data_zbi/driver_config.rs

fidl_data_zbi/
driver_config.rs
