fidl_data_zbi/
driver_config.rs

1// Copyright 2022 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// DO NOT EDIT.
6// Generated from FIDL library `zbi` by zither, a Fuchsia platform tool.
7
8#![allow(unused_imports)]
9
10use bitflags::bitflags;
11use zerocopy::{FromBytes, IntoBytes};
12
13/// ZBI_TYPE_KERNEL_DRIVER item types (for zbi_header_t.extra)
14#[repr(u32)]
15#[derive(Clone, Copy, Debug, Eq, IntoBytes, PartialEq)]
16pub enum KernelDriver {
17    /// 'PSCI'
18    ArmPsci = 0x49435350,
19
20    /// 'PSCS'
21    ArmPsciCpuSuspend = 0x53435350,
22
23    /// 'GIC2'
24    ArmGicV2 = 0x32434947,
25
26    /// 'GIC3'
27    ArmGicV3 = 0x33434947,
28
29    /// 'ATIM'
30    ArmGenericTimer = 0x4d495441,
31
32    /// 'ATMM'
33    ArmGenericTimerMmio = 0x4d4d5441,
34
35    /// 'PL0U'
36    Pl011Uart = 0x55304c50,
37
38    /// 'AMLU'
39    AmlogicUart = 0x554c4d41,
40
41    /// 'AMLH'
42    AmlogicHdcp = 0x484c4d41,
43
44    /// 'DW8U'
45    Dw8250Uart = 0x44573855,
46
47    /// 'RMLH' (typoed, originally intended to by 'AMLR')
48    AmlogicRngV1 = 0x484c4d52,
49
50    /// 'AMLR'
51    AmlogicRngV2 = 0x524c4d41,
52
53    /// 'WD32'
54    Generic32Watchdog = 0x32334457,
55
56    /// 'GENI'
57    GeniUart = 0x494E4547,
58
59    /// '8250'
60    I8250PioUart = 0x30353238,
61
62    /// '825M'
63    I8250Mmio32Uart = 0x4d353238,
64
65    /// '825B'
66    I8250Mmio8Uart = 0x42353238,
67
68    /// 'MMTP'
69    MotmotPower = 0x4d4d5450,
70
71    /// '370P'
72    As370Power = 0x50303733,
73
74    /// 'MNFP'
75    MoonflowerPower = 0x4d4e4650,
76
77    /// 'IMXU'
78    ImxUart = 0x55584d49,
79
80    /// 'PLIC'
81    RiscvPlic = 0x43494C50,
82
83    /// 'RTIM'
84    RiscvGenericTimer = 0x4D495452,
85
86    /// 'PXAU'
87    PxaUart = 0x50584155,
88
89    /// 'EXYU'
90    ExynosUsiUart = 0x45585955,
91
92    /// `QRNG`
93    QcomRng = 0x474E5251,
94}
95
96impl KernelDriver {
97    pub fn from_raw(raw: u32) -> Option<Self> {
98        match raw {
99            0x49435350 => Some(Self::ArmPsci),
100
101            0x53435350 => Some(Self::ArmPsciCpuSuspend),
102
103            0x32434947 => Some(Self::ArmGicV2),
104
105            0x33434947 => Some(Self::ArmGicV3),
106
107            0x4d495441 => Some(Self::ArmGenericTimer),
108
109            0x4d4d5441 => Some(Self::ArmGenericTimerMmio),
110
111            0x55304c50 => Some(Self::Pl011Uart),
112
113            0x554c4d41 => Some(Self::AmlogicUart),
114
115            0x484c4d41 => Some(Self::AmlogicHdcp),
116
117            0x44573855 => Some(Self::Dw8250Uart),
118
119            0x484c4d52 => Some(Self::AmlogicRngV1),
120
121            0x524c4d41 => Some(Self::AmlogicRngV2),
122
123            0x32334457 => Some(Self::Generic32Watchdog),
124
125            0x494E4547 => Some(Self::GeniUart),
126
127            0x30353238 => Some(Self::I8250PioUart),
128
129            0x4d353238 => Some(Self::I8250Mmio32Uart),
130
131            0x42353238 => Some(Self::I8250Mmio8Uart),
132
133            0x4d4d5450 => Some(Self::MotmotPower),
134
135            0x50303733 => Some(Self::As370Power),
136
137            0x4d4e4650 => Some(Self::MoonflowerPower),
138
139            0x55584d49 => Some(Self::ImxUart),
140
141            0x43494C50 => Some(Self::RiscvPlic),
142
143            0x4D495452 => Some(Self::RiscvGenericTimer),
144
145            0x50584155 => Some(Self::PxaUart),
146
147            0x45585955 => Some(Self::ExynosUsiUart),
148
149            0x474E5251 => Some(Self::QcomRng),
150
151            _ => None,
152        }
153    }
154}
155
156/// Kernel driver struct that can be used for simple drivers.
157/// Used by ZBI_KERNEL_DRIVER_PL011_UART, ZBI_KERNEL_DRIVER_AMLOGIC_UART, and
158/// ZBI_KERNEL_DRIVER_GENI_UART, ZBI_KERNEL_DRIVER_I8250_MMIO_UART.
159#[repr(C)]
160#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
161pub struct DcfgSimple {
162    pub mmio_phys: u64,
163    pub irq: u32,
164    pub flags: u32,
165}
166
167#[repr(C)]
168#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
169pub struct KernelDriverIrqFlags(u32);
170
171bitflags::bitflags! {
172    impl KernelDriverIrqFlags : u32 {
173
174        /// When no flag is set, implies no information was obtained, and the
175        /// kernel will apply default configuration as it sees fit.
176        const EDGE_TRIGGERED = 1 << 0;
177        const LEVEL_TRIGGERED = 1 << 1;
178
179        /// Interpretation depends on whether is edge or level triggered.
180        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_LOW`.
181        /// When `EDGE_TRIGGERED` refers to `HIGH_TO_LOW`.
182        const POLARITY_LOW = 1 << 2;
183
184        /// Interpretation depends on whether is edge or level triggered.
185        /// When `LEVEL_TRIGGERED` refers to `ACTIVE_HIGH`.
186        /// When `EDGE_TRIGGERED` refers to `LOW_TO_HIGH`.
187        const POLARITY_HIGH = 1 << 3;
188  }
189}
190
191/// Used by ZBI_KERNEL_DRIVER_I8250_PIO_UART.
192#[repr(C)]
193#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
194pub struct DcfgSimplePio {
195    pub base: u16,
196    pub reserved: u16,
197    pub irq: u32,
198}
199
200/// for ZBI_KERNEL_DRIVER_ARM_PSCI
201#[repr(C)]
202#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
203pub struct DcfgArmPsciDriver {
204    pub use_hvc: u8,
205    pub reserved: [u8; 7],
206    pub shutdown_args: [u64; 3],
207    pub reboot_args: [u64; 3],
208    pub reboot_bootloader_args: [u64; 3],
209    pub reboot_recovery_args: [u64; 3],
210}
211
212/// for ZBI_KERNEL_DRIVER_ARM_GIC_V2
213#[repr(C)]
214#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
215pub struct DcfgArmGicV2Driver {
216    pub mmio_phys: u64,
217    pub msi_frame_phys: u64,
218    pub gicd_offset: u64,
219    pub gicc_offset: u64,
220    pub gich_offset: u64,
221    pub gicv_offset: u64,
222    pub ipi_base: u32,
223    pub optional: u8,
224    pub use_msi: u8,
225    pub reserved: u16,
226}
227
228/// for ZBI_KERNEL_DRIVER_ARM_GIC_V3
229#[repr(C)]
230#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
231pub struct DcfgArmGicV3Driver {
232    pub mmio_phys: u64,
233    pub gicd_offset: u64,
234    pub gicr_offset: u64,
235    pub gicr_stride: u64,
236    pub reserved0: u64,
237    pub ipi_base: u32,
238    pub optional: u8,
239    pub reserved1: [u8; 3],
240}
241
242/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER
243#[repr(C)]
244#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
245pub struct DcfgArmGenericTimerDriver {
246    pub irq_phys: u32,
247    pub irq_virt: u32,
248    pub irq_sphys: u32,
249    pub freq_override: u32,
250}
251
252#[repr(C)]
253#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
254pub struct DcfgArmGenericTimerMmioFrame {
255    /// Base address for the frame's EL1 view.
256    pub mmio_phys_el1: u64,
257
258    /// Base address for the frame's EL0 view.
259    /// This is optional.
260    pub mmio_phys_el0: u64,
261
262    /// IRQ information for physical timer. This is mandatory.
263    pub irq_phys: u32,
264
265    /// Same scheme as `DcfgSimple::irq`. This is mandatory.
266    pub irq_phys_flags: u32,
267
268    /// IRQ information for virtual timer.
269    /// This is optional.
270    /// When is not present both `irq_virt` and `irq_virt_flags` will be zero.
271    pub irq_virt: u32,
272
273    /// Same scheme as `DcfgSimple::irq`.
274    pub irq_virt_flags: u32,
275}
276
277/// for ZBI_KERNEL_DRIVER_ARM_GENERIC_TIMER_MMIO
278#[repr(C)]
279#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
280pub struct DcfgArmGenericTimerMmioDriver {
281    /// Base address of `CNTCTLBase` frame.
282    pub mmio_phys: u64,
283
284    /// The frequency of the main counter for the timer.
285    pub frequency: u32,
286
287    /// Bitmask containing the set of active frames.
288    /// The `i-th` frame is considered active iff the `i`-th bit is set.
289    /// Note: While there may be up to 8 frames, both missing and disabled frames are treated
290    /// as inactive. Disabled frame information will be present, while missing frames will be zeroed.
291    pub active_frames_mask: u8,
292    pub reserved0: [u8; 3],
293
294    /// Information for each individual frame.
295    /// Inactive frames must be zero-filled.
296    pub frames: [DcfgArmGenericTimerMmioFrame; 8],
297}
298
299/// for ZBI_KERNEL_DRIVER_AMLOGIC_HDCP
300#[repr(C)]
301#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
302pub struct DcfgAmlogicHdcpDriver {
303    pub preset_phys: u64,
304    pub hiu_phys: u64,
305    pub hdmitx_phys: u64,
306}
307
308/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V1
309/// for ZBI_KERNEL_DRIVER_AMLOGIC_RNG_V2
310#[repr(C)]
311#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
312pub struct DcfgAmlogicRngDriver {
313    pub rng_data_phys: u64,
314    pub rng_status_phys: u64,
315    pub rng_refresh_interval_usec: u64,
316}
317
318/// Defines a register write action for a generic kernel watchdog driver.  An
319/// action consists of the following steps.
320///
321/// 1) Read from the register located a physical address |addr|
322/// 2) Clear all of the bits in the value which was read using the |clr_mask|
323/// 3) Set all of the bits in the value using the |set_mask|
324/// 4) Write this value back to the address located at addr
325#[repr(C)]
326#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
327pub struct DcfgGeneric32WatchdogAction {
328    pub addr: u64,
329    pub clr_mask: u32,
330    pub set_mask: u32,
331}
332
333#[repr(C)]
334#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
335pub struct KernelDriverGeneric32WatchdogFlags(u32);
336
337bitflags::bitflags! {
338    impl KernelDriverGeneric32WatchdogFlags : u32 {
339        const ENABLED = 1 << 0;
340  }
341}
342
343/// 1ms
344pub const KERNEL_DRIVER_GENERIC32_WATCHDOG_MIN_PERIOD: i64 = 1000000;
345
346/// Definitions of actions which may be taken by a generic 32 bit watchdog timer
347/// kernel driver which may be passed by a bootloader.  Field definitions are as
348/// follows.
349#[repr(C)]
350#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
351pub struct DcfgGeneric32Watchdog {
352    /// The address and masks needed to "pet" (aka, dismiss) a hardware watchdog timer.
353    pub pet_action: DcfgGeneric32WatchdogAction,
354
355    /// The address and masks needed to enable a hardware watchdog timer.  If enable
356    /// is an unsupported operation, the addr of the |enable_action| shall be zero.
357    pub enable_action: DcfgGeneric32WatchdogAction,
358
359    /// The address and masks needed to disable a hardware watchdog timer.  If
360    /// disable is an unsupported operation, the addr of the |disable_action| shall
361    /// be zero.
362    pub disable_action: DcfgGeneric32WatchdogAction,
363
364    /// The period of the watchdog timer given in nanoseconds.  When enabled, the
365    /// watchdog timer driver must pet the watch dog at least this often.  The value
366    /// must be at least 1 mSec, typically much larger (on the order of a second or
367    /// two).
368    pub watchdog_period_nsec: i64,
369
370    /// Storage for additional flags.  Currently, only one flag is defined,
371    /// "FLAG_ENABLED".  When this flag is set, it indicates that the watchdog timer
372    /// was left enabled by the bootloader at startup.
373    pub flags: KernelDriverGeneric32WatchdogFlags,
374    pub reserved: u32,
375}
376
377/// for ZBI_KERNEL_DRIVER_RISCV_PLIC
378#[repr(C)]
379#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
380pub struct DcfgRiscvPlicDriver {
381    /// Physical address of the PLIC MMIO region.
382    pub mmio_phys: u64,
383
384    /// Size in bytes of the PLIC MMIO region.
385    pub size_bytes: u32,
386
387    /// Number of supported IRQs.
388    pub num_irqs: u32,
389}
390
391/// for ZBI_KERNEL_DRIVER_RISCV_GENERIC_TIMER
392#[repr(C)]
393#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
394pub struct DcfgRiscvGenericTimerDriver {
395    pub freq_hz: u32,
396    pub reserved: u32,
397}
398
399#[repr(C)]
400#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
401pub struct ArmPsciCpuSuspendStateFlags(u32);
402
403bitflags::bitflags! {
404    impl ArmPsciCpuSuspendStateFlags : u32 {
405
406        /// If set, when entering the associated low power state the CPU's architectural timer will be
407        /// turned off, making it an unsuitable source for exiting the low power state.
408        /// A different source must be programmed.
409        const LOCAL_TIMER_STOPS = 1 << 0;
410
411        /// If set, the PSCI CPU Suspend operation will affect the entire power domain, implying all other
412        /// CPUs of the power domain must be in a low power mode. That is, the last CPU in the power
413        /// domain is the one to enter this power state.
414        const TARGETS_POWER_DOMAIN = 1 << 1;
415  }
416}
417
418/// The ZBI_KERNEL_DRIVER_ARM_PSCI_CPU_SUSPEND's payload consists on any number of
419/// `DcfgArmPsciCpuSuspendState` entries.
420///
421/// The length of the item is `sizeof(zbi_dcfg_arm_psci_cou_suspend_state_t)` times the number of
422/// entries. Each entry describes an 'idle state' that can be entered through PSCI CPU Suspend call.
423///
424/// Entries in the table may be in any order, and only a single item of type
425/// ZBI_KERNEL_DRIVER_ARM_PSCI_CPU_SUSPEND should be present in the ZBI.
426#[repr(C)]
427#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
428pub struct DcfgArmPsciCpuSuspendState {
429    /// Unique identifier representing this suspend state.
430    pub id: u32,
431
432    /// PSCI power_state as described in "Section 5.4.2. of Arm Power State Coordination Interface"
433    /// v1.3.
434    pub power_state: u32,
435    pub flags: ArmPsciCpuSuspendStateFlags,
436
437    /// Latency in microseconds to enter the low power state.
438    pub entry_latency_us: u32,
439
440    /// Latency in microseconds to exit the low power state.
441    pub exit_latency_us: u32,
442
443    /// Minimum time in microseconds, including `entry_latency`, to stay in this low power state.
444    /// Spending less time would be inefficient energy-wise.
445    pub min_residency_us: u32,
446}
447
448#[repr(C)]
449#[derive(IntoBytes, FromBytes, Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
450pub struct QcomRngFlags(u32);
451
452bitflags::bitflags! {
453    impl QcomRngFlags : u32 {
454
455        /// The driver has been handed off, configured and initialized.
456        const ENABLED = 1 << 0;
457  }
458}
459
460#[repr(C)]
461#[derive(Clone, Copy, Debug, Eq, FromBytes, IntoBytes, PartialEq)]
462pub struct DcfgQcomRng {
463    /// Base address of the register banks for the device.
464    pub mmio_phys: u64,
465    pub flags: QcomRngFlags,
466    pub reserved: [u8; 4],
467}
fidl_data_zbi/driver_config.rs

fidl_data_zbi/
driver_config.rs
