class Request

Defined at line 955 of file fidling/gen/sdk/fidl/fuchsia.hardware.usb.request/fuchsia.hardware.usb.request/cpp/fidl/fuchsia.hardware.usb.request/cpp/wire_types.h

Requests passed over fuchsia.hardware.usb.endpoint.Endpoint.

See fuchsia.hardware.usb.endpoint.Endpoint::QueueRequests for more details.

Public Methods

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_usb_request::wire::Request> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_usb_request::wire::Request> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_usb_request::wire::Request>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

void Allocate (::fidl::AnyArena & allocator)

void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_usb_request::wire::Request>> && frame_ptr)

void Request ()

Defined at line 957 of file fidling/gen/sdk/fidl/fuchsia.hardware.usb.request/fuchsia.hardware.usb.request/cpp/fidl/fuchsia.hardware.usb.request/cpp/wire_types.h

void Request (const Request & other)

Defined at line 958 of file fidling/gen/sdk/fidl/fuchsia.hardware.usb.request/fuchsia.hardware.usb.request/cpp/fidl/fuchsia.hardware.usb.request/cpp/wire_types.h

void Request (Request && other)

Defined at line 960 of file fidling/gen/sdk/fidl/fuchsia.hardware.usb.request/fuchsia.hardware.usb.request/cpp/fidl/fuchsia.hardware.usb.request/cpp/wire_types.h

void _CloseHandles ()

::fidl::VectorView< ::fuchsia_hardware_usb_request::wire::BufferRegion> & data ()

Data. This array is consumed in-order, and allows for scatter/gather semantics across

physically non-contiguous regions of a large buffer.

bool has_data ()

bool & defer_completion ()

Indicates not to complete this Request when done unless it failed.

All Requests up to the next defer_completion == false are responded to as one unit.

bool has_defer_completion ()

::fuchsia_hardware_usb_request::wire::RequestInfo & information ()

Extra information needed for Request.

bool has_information ()

Request & operator= (const Request & other)

Defined at line 959 of file fidling/gen/sdk/fidl/fuchsia.hardware.usb.request/fuchsia.hardware.usb.request/cpp/fidl/fuchsia.hardware.usb.request/cpp/wire_types.h

Request & operator= (Request && other)

Defined at line 961 of file fidling/gen/sdk/fidl/fuchsia.hardware.usb.request/fuchsia.hardware.usb.request/cpp/fidl/fuchsia.hardware.usb.request/cpp/wire_types.h

bool & short_ ()

True if this is a short transfer sending less than what the receiver is

expecting. Controllers ensure this transfer is terminated by a short

packet.

Interpreted as false if absent.

bool has_short ()

Request & set_data (::fidl::ObjectView< ::fidl::VectorView< ::fuchsia_hardware_usb_request::wire::BufferRegion>> elem)

Request & set_data (std::nullptr_t )

Request & clear_data ()

Request & set_defer_completion (bool elem)

Request & clear_defer_completion ()

Request & set_information (::fidl::ObjectView< ::fuchsia_hardware_usb_request::wire::RequestInfo> elem)

Request & set_information (std::nullptr_t )

Request & clear_information ()

Request & set_short_ (bool elem)

Request & clear_short ()

void Request (::fidl::AnyArena & allocator)

void Request (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_usb_request::wire::Request>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void ~Request ()

Defined at line 963 of file fidling/gen/sdk/fidl/fuchsia.hardware.usb.request/fuchsia.hardware.usb.request/cpp/fidl/fuchsia.hardware.usb.request/cpp/wire_types.h

Friends

class WireTableBaseBuilder

class WireTableBaseBuilder