class DeviceBaseInfo

class DeviceBaseInfo

Defined at line 318 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

Network device base info.

Public Methods

void DeviceBaseInfo ()

Defined at line 320 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

void DeviceBaseInfo (const DeviceBaseInfo & other)

Defined at line 321 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

bool IsEmpty ()

Returns whether no field is set.

bool HasUnknownData ()

Returns whether the table references unknown fields.

::fidl::WireTableBuilder< ::fuchsia_hardware_network::wire::DeviceBaseInfo> Builder (::fidl::AnyArena & arena)

Return a builder that by defaults allocates of an arena.

::fidl::WireTableExternalBuilder< ::fuchsia_hardware_network::wire::DeviceBaseInfo> ExternalBuilder (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_network::wire::DeviceBaseInfo>> frame)

Return a builder that relies on explicitly allocating |fidl::ObjectView|s.

bool has_tx_depth ()
uint32_t & buffer_alignment ()

Alignment requirement for buffers in the data VMO.

All buffers in the data VMO *must* be aligned to `buffer_alignment`

relative to the start of the VMO. `buffer_alignment == 0` is never

reported. Required.

bool has_buffer_alignment ()
uint32_t & max_buffer_length ()

Maximum supported length of buffers in the data VMO, in bytes.

Absent if no maximum buffer length is defined. Must be nonzero.

bool has_max_buffer_length ()
uint32_t & min_rx_buffer_length ()

The minimum rx buffer length required for device. Required.

bool has_min_rx_buffer_length ()
uint32_t & min_tx_buffer_length ()

The minimum tx buffer length required for the device. Required.

This value accounts only for tx payload length, `min_tx_buffer_head` and

`min_tx_buffer_tail` are not part of this value.

Clients must zero pad outgoing frames to meet the required minimum

length.

bool has_min_tx_buffer_length ()
uint16_t & min_tx_buffer_head ()

The number of bytes the device requests be free as `head` space in a tx

buffer. Required.

bool has_min_tx_buffer_head ()
uint16_t & min_tx_buffer_tail ()

The amount of bytes the device requests be free as `tail` space in a tx

buffer. Required.

bool has_min_tx_buffer_tail ()
uint8_t & max_buffer_parts ()

Maximum descriptor chain length accepted by the device. Required.

bool has_max_buffer_parts ()
uint16_t & min_rx_buffers ()

Minimum amount of Rx buffers the client needs to prepare for the

network device. Client should use this information to select its

VMO sizes if using multi-VMO support.

bool has_min_rx_buffers ()
DeviceBaseInfo & operator= (const DeviceBaseInfo & other)

Defined at line 322 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

void DeviceBaseInfo (DeviceBaseInfo && other)

Defined at line 323 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

DeviceBaseInfo & operator= (DeviceBaseInfo && other)

Defined at line 324 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

uint16_t & rx_depth ()

Maximum number of items in rx FIFO (per session). Required.

`rx_depth` is calculated based on the size of the actual backing

hardware rx queue.

bool has_rx_depth ()
uint16_t & tx_depth ()

Maximum number of items in tx FIFO (per session). Required.

`tx_depth` is calculated based on the size of the actual backing

hardware tx queue.

DeviceBaseInfo & set_rx_depth (uint16_t elem)
DeviceBaseInfo & clear_rx_depth ()
DeviceBaseInfo & set_tx_depth (uint16_t elem)
DeviceBaseInfo & clear_tx_depth ()
DeviceBaseInfo & set_buffer_alignment (uint32_t elem)
DeviceBaseInfo & clear_buffer_alignment ()
DeviceBaseInfo & set_max_buffer_length (uint32_t elem)
DeviceBaseInfo & clear_max_buffer_length ()
DeviceBaseInfo & set_min_rx_buffer_length (uint32_t elem)
DeviceBaseInfo & clear_min_rx_buffer_length ()
DeviceBaseInfo & set_min_tx_buffer_length (uint32_t elem)
DeviceBaseInfo & clear_min_tx_buffer_length ()
DeviceBaseInfo & set_min_tx_buffer_head (uint16_t elem)
DeviceBaseInfo & clear_min_tx_buffer_head ()
DeviceBaseInfo & set_min_tx_buffer_tail (uint16_t elem)
DeviceBaseInfo & clear_min_tx_buffer_tail ()
DeviceBaseInfo & set_max_buffer_parts (uint8_t elem)
DeviceBaseInfo & clear_max_buffer_parts ()
DeviceBaseInfo & set_min_rx_buffers (uint16_t elem)
DeviceBaseInfo & clear_min_rx_buffers ()
void DeviceBaseInfo (::fidl::AnyArena & allocator)
void DeviceBaseInfo (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_network::wire::DeviceBaseInfo>> && frame)

This constructor allows a user controlled allocation (not using a Arena).

It should only be used when performance is key.

As soon as the frame is given to the table, it must not be used directly or for another table.

void Allocate (::fidl::AnyArena & allocator)
void Init (::fidl::ObjectView< ::fidl::WireTableFrame< ::fuchsia_hardware_network::wire::DeviceBaseInfo>> && frame_ptr)
void ~DeviceBaseInfo ()

Defined at line 326 of file fidling/gen/sdk/fidl/fuchsia.hardware.network/fuchsia.hardware.network/cpp/fidl/fuchsia.hardware.network/cpp/wire_types.h

Friends

class WireTableBaseBuilder
class WireTableBaseBuilder